Parallel Inductor Segmentation for Low Parasitic Resistance
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Solution Overview
Problem
Current inductor designs in VLSI chips face challenges in reducing parasitic resistance and eddy current loss, leading to high power dissipation and low quality factor, which affects the efficiency of clock networks in mobile and desktop systems.
Innovation Solution
The solution involves connecting additional inductors in parallel across the leads of an existing inductor in an LC tank circuit, utilizing magnetic coupling to maintain the original inductance value while reducing parasitic resistance, and segmenting inductors into parallel strips to minimize eddy current loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If additional inductors are connected in parallel to reduce parasitic resistance, then power dissipation decreases, but the inductance value changes
Solution Approach 1:
The inductor is segmented into multiple parallel inductive elements (first and second inductors) that are magnetically coupled. This segmentation allows the parasitic resistance to be distributed across multiple paths, reducing total power dissipation while maintaining the required inductance value through magnetic coupling between the segments.
Solution Approach 2:
Magnetic coupling acts as an intermediary mechanism between the parallel inductive elements. The magnetic field serves as a mediator that transfers energy between the first and second inductors, allowing them to work together to maintain the original inductance value while benefiting from reduced parasitic resistance through parallel connection.
2Reliability
If inductors are segmented into parallel strips to reduce eddy current loss, then quality factor increases, but manufacturing complexity increases
Solution Approach 1:
The inductor is segmented into multiple parallel strips or elements that can be fabricated using standard CMOS metallization layers. This segmentation reduces eddy current paths while maintaining inductance through magnetic coupling, and the segmented structure can be implemented using conventional multi-layer metal fabrication processes.
Solution Approach 2:
The inductor structure transitions from a planar two-dimensional layout to a three-dimensional multi-layer configuration. By utilizing vertical stacking of metal layers with magnetic coupling between layers, the design achieves reduced eddy current loss through dimensional expansion while remaining compatible with standard CMOS fabrication processes.
3Reliability
If magnetic coupling is used to maintain inductance value, then inductance stability is improved, but device complexity increases
Solution Approach 1:
Magnetic coupling serves as an intermediary mechanism that automatically maintains inductance stability without requiring complex control circuits. The magnetic field naturally couples the parallel inductive elements, providing passive inductance stabilization that avoids the need for active feedback or complex control logic.
Solution Approach 2:
The magnetically coupled inductor structure is self-regulating in terms of inductance maintenance. The magnetic coupling between parallel elements automatically compensates for changes in individual element parameters, providing self-stabilization of the total inductance value without external intervention or complex control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases the parasitic resistance and eddy current loss, enhancing the quality factor and reducing power dissipation in clock networks, thereby improving the efficiency and performance of clock signal distribution in VLSI chips.
Implementation Method 1
The transformer, which utilizes a magnetic coupling coefficient, k, between the two coils to increase the equivalent inductance
Implementation Method 2
Another method to increase the Q for designs above 1 GHz is to reduce the induced eddy current in the conductor of the inductor
Data Source
AI summary
Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.