Parallel Integral Image Algorithm for Many-Core CPUs
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Solution Overview
Problem
Existing methods for computing the integral image on multi-core architectures face challenges in minimizing non-sequential memory accesses, maximizing parallelism, and maintaining work efficiency, particularly due to limitations in memory bandwidth and synchronization overhead.
Innovation Solution
The approach involves splitting the image into non-overlapping tiles and using a tiled row-major in-memory representation, with computations parallelized per tile, and employing the Single-Pass Sum Algorithm and Two-Dimensional Inclusive Parallel Prefix Sum (2D-IPPS) algorithm to minimize non-sequential memory accesses and optimize memory bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If GPU-based approaches are used for integral image computation, then memory access performance is optimized through hardware coalescing, but the degree of parallelism is limited and work efficiency is compromised
Solution Approach 1:
The image is divided into multiple non-overlapping tiles that can be processed independently in parallel. Each tile is further subdivided into blocks that can be assigned to different threads, enabling fine-grained parallelism while maintaining sequential memory access patterns within each block. This segmentation allows the algorithm to achieve high parallelism on commodity CPUs without relying on GPU hardware coalescing.
2Productivity
If parallelization is increased to maximize degree of parallelism, then computational speed improves, but non-sequential memory accesses increase causing performance deterioration
Solution Approach 1:
The algorithm transforms the 2D integral image computation into a series of 1D prefix sum operations by processing the image in a tiled manner. Within each tile, computations are organized to access memory sequentially along rows and columns, eliminating random access patterns. This dimensional transformation allows high parallelism across tiles while maintaining sequential access within each computational unit.
3Productivity
If tiling is used to increase parallelism, then degree of parallelism improves, but synchronization overhead and memory bandwidth utilization are compromised
Solution Approach 1:
The algorithm performs preliminary computations within each tile to compute partial integral images and boundary sums before combining results. By pre-computing these intermediate values in parallel within local memory, the algorithm minimizes the need for synchronization and inter-tile communication. This preliminary action allows tiles to be processed independently and combined with minimal overhead.
Data Source
AI summary
Techniques are provided herein for generating an integral image of an input image in parallel across the cores of a multi-core processor. The input image is split into a plurality of tiles, each of which is stored in a scratchpad memory associated with a distinct core. At each tile, a partial integral image of the tile is first computed over the tile, using a Single-Pass Algorithm. This is followed by aggregating partial sums belonging to subsets of tiles using a 2D Inclusive Parallel Prefix Algorithm. A summation is finally performed over the aggregated partial sums to generate the integral image over the entire input image.