Parallel Interface Per-Pin Deskew for Clock-Data Skew Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, skew between reference clock signals and data signals in parallel interface systems limits data transmission rates due to phase differences, reducing voltage and time margins, and existing deskew methods either require additional circuitry or prolong system performance.
Innovation Solution
A semiconductor device with a reference clock transmitting block, transceiver blocks, and a per-pin deskew block that adjusts the phase of the transmitting sampling clock signal based on phase skew information from training data or received phase skew information to reduce skew between the reference clock and data signals, combining per-pin deskew using clock and data recovery (CDR) and training data methods to minimize circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If per-pin deskew using CDR is implemented, then skew reduction precision is improved, but device complexity and occupied chip area increase
Solution Approach 1:
The patent segments the deskew function into two distinct modes: training data mode for initial skew calibration and CDR mode for dynamic skew compensation. This segmentation allows the system to use the simpler training data method for static skew reduction while reserving the more complex CDR mechanism only for dynamic conditions, thereby reducing overall circuit complexity while maintaining skew reduction precision
Solution Approach 2:
The patent implements dynamic mode switching between training data deskew and CDR deskew based on operational requirements. The system transitions from static training data-based skew reduction to dynamic CDR-based skew reduction when needed, allowing the deskew mechanism to adapt its complexity level to the actual operational demands, thus optimizing the balance between precision and device complexity
2Device complexity
If per-pin deskew using training data is used, then device complexity is reduced, but adaptability to dynamic skew conditions deteriorates
Solution Approach 1:
The patent makes the deskew system dynamic by implementing mode switching capability. The system can transition from static training data deskew to dynamic CDR deskew based on operational requirements, enabling adaptability to changing skew conditions while maintaining simplicity when dynamic adaptation is not needed
Solution Approach 2:
The patent incorporates feedback mechanisms in CDR mode where the received data is continuously monitored and used to adjust the sampling clock phase in real-time. This feedback loop enables the system to adapt to dynamic skew conditions by continuously correcting phase errors based on actual received signal quality
3Productivity
If data transmission rate is increased, then productivity is improved, but skew between clock and data signals increases
Solution Approach 1:
The patent performs preliminary skew calibration using training data before actual high-speed data transmission begins. By pre-adjusting the sampling clock phase based on training data patterns, the system establishes optimal phase alignment before high-rate transmission, thereby maintaining phase alignment accuracy even at increased transmission rates
Solution Approach 2:
The patent implements continuous feedback-based phase adjustment during high-speed transmission through CDR mechanisms. The system monitors received data quality in real-time and dynamically adjusts the sampling clock phase to compensate for skew that increases with transmission rate, thereby maintaining phase alignment accuracy at high productivity levels
4Reliability
If voltage margin and time margin are increased to compensate for skew, then reliability is improved, but data transmission rate is limited
Solution Approach 1:
The patent performs preliminary phase calibration using training data to optimize sampling clock alignment before high-speed transmission. By establishing correct phase alignment in advance, the system achieves reliable data identification at high transmission rates without requiring excessive voltage or time margins, thus maintaining both reliability and productivity
Data Source
AI summary
A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.