Parallel Interleave Circuit With Double Buffer Address Reordering
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Solution Overview
Problem
Conventional interleave circuits face challenges in throughput reduction and circuit implementation difficulties, especially when dealing with large block sizes, which affect the stability and speed of error correction in Quantum Key Distribution (QKD) systems.
Innovation Solution
An interleave circuit and communication device are designed with a reordering circuit and address calculation circuit to reorder data in parallel, using a double buffer operation with memories of practical size, allowing high throughput even with large block sizes, and incorporating a deinterleave circuit for data reordering in the original order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block interleave processing is performed to ensure stable error correction and improve information transmission speed, then error correction stability is improved, but throughput is reduced and circuit implementation becomes difficult
Solution Approach 1:
The patent segments the block interleave processing into two distinct stages: an interleave circuit that performs initial reordering, and a deinterleave circuit that performs final reordering. This segmentation allows the system to maintain error correction stability while improving throughput by enabling parallel processing and reducing bottlenecks in the error correction pipeline.
Solution Approach 2:
The interleave circuit performs preliminary reordering of data blocks before error correction processing. By pre-organizing the data in an interleaved format, the system prepares the data structure needed for stable error correction while allowing subsequent processing stages to operate efficiently on the pre-processed data.
2Speed
If block interleave processing is performed to improve information transmission speed, then information transmission speed is improved, but circuit implementation becomes difficult
Solution Approach 1:
The patent divides the complex block interleave processing into separate interleave and deinterleave circuits. Each circuit handles a specific portion of the reordering operation, making the individual circuit designs simpler and more implementable while maintaining the overall high-speed processing capability through coordinated operation of both circuits.
Solution Approach 2:
The patent introduces an intermediary memory structure that stores the interleaved data between the interleave circuit and the deinterleave circuit. This intermediary storage mechanism simplifies the circuit implementation by providing a buffer that decouples the timing and complexity requirements of the two reordering operations, enabling high-speed processing without excessive circuit complexity.
3Reliability
If conventional interleave circuits are used to perform block interleave processing, then error correction stability is improved, but throughput reduction occurs
Solution Approach 1:
The patent merges the interleave and deinterleave operations into a unified error correction system where both circuits operate in coordination. This merging allows the system to maintain the error correction stability provided by block interleave processing while achieving higher throughput through optimized data flow and parallel processing capabilities of the combined circuit architecture.
Data Source
AI summary
According to an embodiment, an interleave circuit includes a reordering circuit and an address calculation circuit. The reordering circuit is configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of output data each containing n bits input in cycles different from each other. The address calculation circuit is configured to calculate write addresses for writing the n-pieces of output data into a first storage device and read addresses for reading out the n-pieces of output data from the first storage device.