Parallel Bit Interleaving Across Cyclic Blocks for Lower Latency
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, leading to impaired parallelism and limited bit interleaver configurations, particularly when the number of cyclic blocks is not a multiple of the interleaver matrix columns, resulting in increased latency and suboptimal performance.
Innovation Solution
A bit interleaving method that divides codewords into sections, with each constellation word comprising bits from multiple cyclic blocks, ensuring that all bits of a section are mapped to only Q constellation words associated with that section, and applying a bit permutation process that maps M bits from different cyclic blocks to each constellation word, optimizing the interleaving process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of interleaver matrix columns
Solution Approach 1:
The patent divides the codeword into multiple sections, where each section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be organized in a structured manner, enabling efficient parallel processing by ensuring that each section can be independently processed without requiring the total number of cyclic blocks to be a multiple of the interleaver matrix columns, thus reducing latency while maintaining high interleaving efficiency.
2Adaptability or versatility
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but the number of available bit interleaver configurations is limited
Solution Approach 1:
The patent introduces a configurable section structure where the number of cyclic blocks per section and the mapping relationships can be dynamically adjusted based on the specific QC-LDPC code parameters and system requirements. This dynamic configuration approach enables a wide range of bit interleaver configurations to be implemented without being constrained by fixed structural requirements, thereby increasing adaptability while managing device complexity through systematic design.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.