Parallel Intra-Prediction Video Decoding via Control Maps

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Solution Overview

Problem

Most personal computers lack the computational capability to decode high-density video data compressed using high compression ratio schemes like H.264, such as those found on Blu-ray discs, due to inefficient use of modern processors' parallelism and the need for additional decoding hardware.

Innovation Solution

A system with a processing unit featuring multiple processing pipelines and a driver that generates intermediate control maps to optimize parallel processing of video data, allowing for layered decoding of video frames and minimizing CPU usage, thereby enhancing graphics processing unit (GPU) performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential macro block decoding is used, then decoding accuracy is maintained, but processing speed and parallelism utilization deteriorate

Engineering Contradiction:
Improvedecoding speedVSAvoidcontrol overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary classification of macro blocks into independent and dependent types before decoding. This allows the system to pre-identify which blocks can be processed in parallel and which require sequential processing, thereby optimizing the use of multiple processing pipelines while maintaining correct decoding dependencies.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the video frame into multiple macro blocks and further divides them into independent and dependent groups. This segmentation enables different processing strategies to be applied to different segments, with independent blocks processed in parallel across multiple pipelines and dependent blocks processed sequentially, thus improving overall decoding productivity.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If high compression ratio schemes like H.264 are used, then data storage and transmission efficiency is improved, but computational complexity increases

Engineering Contradiction:
Improvecompression ratioVSAvoidcomputational complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent replaces traditional CPU-based sequential decoding with a GPU-based parallel processing system. The complex computational tasks of H.264 decoding are distributed across multiple processing pipelines in the GPU, which can simultaneously process multiple macro blocks, thereby reducing the computational burden on the CPU and leveraging the parallel architecture to handle the high computational complexity of high compression ratio schemes.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If dedicated decoding hardware is added to PCs, then decoding capability for high-density media is improved, but system complexity and cost increase

Engineering Contradiction:
Improvedecoding capabilityVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the GPU, which is already present in most PCs for graphics processing, multi-functional by enabling it to perform video decoding tasks in addition to its traditional graphics rendering functions. This eliminates the need for dedicated decoding hardware while providing robust decoding capability for high-density media, as the GPU's parallel architecture is well-suited for the computational demands of H.264 decoding.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9565433B2System for parallel intra-prediction decoding of video data
Publication Date: 2017.02.07 ATI TECHNOLOGIES ULC
  • US9565433B2 patent drawing
  • US9565433B2 patent drawing
  • US9565433B2 patent drawing

AI summary

A system for decoding video data includes a processing unit. The processing unit includes a plurality of processing pipelines and a driver. The driver includes a decoder configured to generate a plurality of intermediate control maps containing control information including an indication of which macro blocks or portions of macro blocks may be processed in parallel in the plurality of processing pipelines.