Parallel Inverter Phase Interleaving for DC Bus Ripple Control
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Solution Overview
Problem
Existing systems for controlling parallel inverters coupled to a common DC bus struggle to optimally manage or minimize DC bus current due to the limitations of fixed interleaving angles, which do not account for all engineering factors.
Innovation Solution
A system that estimates an interleaving phase shift angle using a particle swarm optimization (PSO) model, incorporating a modulation index estimator and optional ripple current observer to dynamically adjust the phase shift and minimize DC bus current, with a capacitor for filtering ripple current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a fixed interleaving angle is used based on the number of parallel inverters, then the DC ripple current can be reduced to some extent, but the DC bus current cannot be optimally managed or minimized due to engineering factors not accounted for in the calculation
Solution Approach 1:
The patent applies dynamics by transitioning from a static fixed interleaving angle to a dynamic adaptive interleaving angle that is continuously adjusted based on real-time system conditions. The controller monitors DC bus current, modulation indices, and operating parameters to dynamically optimize the interleaving angle, enabling the system to adapt to changing loads and operating conditions while minimizing DC ripple current effectively
Solution Approach 2:
The patent implements parameter changes by modifying the interleaving angle parameter based on real-time measurements of DC bus current, modulation indices, and system operating conditions. The controller adjusts this critical parameter dynamically to optimize DC bus current management, transforming the fixed parameter approach into a variable parameter system that responds to actual system needs
2Power
If multiple inverters are coupled to a common DC bus, then the system capacity is increased, but the DC bus current ripple increases requiring larger capacitor sizes
Solution Approach 1:
The patent applies feedback by continuously monitoring the DC bus current, capacitor voltage, and inverter operating parameters, then using this information to adjust the interleaving angle in real-time. The controller receives feedback about the actual DC bus current ripple and dynamically optimizes the phase shift between inverters to minimize the ripple, thereby reducing the required capacitor size for a given system capacity
Solution Approach 2:
The patent implements preliminary action by proactively adjusting the interleaving angle before excessive DC bus current ripple develops. The controller predicts optimal interleaving angles based on anticipated load conditions and system parameters, making preemptive adjustments that prevent large current ripples from occurring, thus reducing the need for oversized capacitors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively manages and minimizes DC bus current by dynamically adjusting the interleaving phase shift angle, improving the efficiency of parallel inverter operations and reducing ripple current.
Implementation Method 1
A capacitor has a known capacitance value for filtering the ripple current of the DC voltage bus
Data Source
AI summary
A capacitor has a known capacitance value for filtering the ripple current of the DC voltage bus. A first modulation index estimator is configured to estimate a first modulation index of the first inverter. A second modulation index estimator configured to estimate a second modulation index of the second inverter. A current estimator is configured to estimate an interleaving phase shift angle associated with a respective one of a set of inverters based on the known capacitance value of the capacitor, the estimated first modulation index, the estimated second modulation index, the first control input and the second control input.