Parallel Output Short Circuit Current Testing for IC Packages
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Solution Overview
Problem
The existing methods for testing output short circuit current in integrated circuits are time-consuming due to the serial pin-by-pin approach, which is inefficient for high-density devices with a large number of output pins, especially in ATE environments where power supply and current measurement limitations restrict parallel testing.
Innovation Solution
A new method involving a test board design and the use of double throw relays and resistors to simulate a short circuit condition across multiple output pins simultaneously, allowing for parallel measurement of current limiting circuits, thereby reducing test time by measuring voltage drops across resistors using ATE channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If IOS testing is performed serially pin by pin using conventional ATE methods, then current measurement accuracy is maintained, but test time increases significantly
Solution Approach 1:
The testing process is segmented into two distinct phases: (1) a calibration phase where a known test current is applied and measured to establish a reference relationship between ATE channel readings and actual currents, and (2) a measurement phase where the calibrated ATE channels measure currents during IOS testing. This segmentation allows the system to achieve both speed and accuracy by pre-establishing measurement relationships.
Solution Approach 2:
The patent performs preliminary calibration actions before the actual IOS testing begins. The ATE channels are pre-configured with test currents, and the relationship between channel readings and actual currents is pre-determined through calibration measurements. This preliminary setup enables rapid subsequent measurements without repeating the calibration process for each pin.
2Productivity
If parallel testing of multiple output pins is attempted using conventional ATE methods, then test time is reduced, but power supply and current measurement limitations prevent accurate measurement
Solution Approach 1:
The patent changes the measurement parameter from direct current measurement to voltage measurement across known resistors. By measuring voltage drops across precision resistors connected to each output pin and using Ohm's law (I=V/R), the system can accurately determine currents even when multiple pins are tested in parallel, overcoming the ATE's current measurement limitations.
Solution Approach 2:
The patent introduces intermediary components (precision resistors and voltage measurement circuits) between the output pins and the ATE measurement system. These intermediaries convert current information into voltage signals that can be accurately measured by the ATE channels, enabling parallel current measurement capability.
3Adaptability or versatility
If the number of output pins increases in high-density devices, then device functionality is improved, but the complexity and time required for IOS testing increases
Solution Approach 1:
The patent creates a universal testing methodology that can handle any number of output pins using the same basic approach. The calibrated ATE channels can simultaneously measure currents on multiple pins regardless of the total pin count, making the testing system adaptable to high-density devices without requiring proportional increases in testing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required for output short circuit current testing from several seconds to tens of milliseconds, regardless of the number of output pins, by enabling simultaneous testing of all pins and improving test efficiency and cost-effectiveness.
Implementation Method 1
A new method involving a test board design and the use of double throw relays and resistors to simulate a short circuit condition across multiple output pins simultaneously
Implementation Method 2
allowing for parallel measurement of current limiting circuits, thereby reducing test time by measuring voltage drops across resistors using ATE channels
Data Source
AI summary
An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value.