Parallel Lane Check Data Encoding for Low-Latency Reordering
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Solution Overview
Problem
Existing data processing systems face increased circuit area, cost, complexity, and latency due to the necessity of generating and using check data for error detection and correction, particularly in reordering payload data which adds to the critical path and processing latency.
Innovation Solution
The use of multiple lane encoders operating in parallel to generate lane check data using a common processing operation, with mask circuitry to combine these into C-bit payload check data, reducing latency and eliminating the need for sequential reordering and re-encoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial processing with multiplexer and decoder is used to generate check data, then error detection and correction capability is provided, but processing latency and circuit complexity increase
Solution Approach 1:
The payload data is divided into N separate M-bit words that are processed independently by N parallel lane encoders. Each lane encoder processes its respective M-bit word simultaneously, generating N separate check data values that are then combined by mask circuitry to produce the final C-bit check data. This segmentation enables parallel processing and eliminates the sequential bottlenecks of the serial approach.
Solution Approach 2:
The invention transitions from a single-dimensional serial processing approach to a multi-dimensional parallel architecture by introducing N processing lanes. The lane encoders operate in parallel across the N dimensions, and the mask circuitry combines results along the C-bit dimension, effectively adding dimensional complexity to reduce temporal latency.
2Adaptability or versatility
If reordering circuitry is added to handle different data orders, then adaptability to different data formats is improved, but critical path delay and processing latency increase
Solution Approach 1:
The lane encoders are designed to process M-bit words in any order without requiring prior reordering, as each encoder independently processes its assigned data word. The mask circuitry then combines the results to produce check data that is valid regardless of the input word order. This preliminary design decision eliminates the need for intermediate reordering circuitry and reduces critical path delay.
3Reliability
If check data generation circuits are added to provide error resilience, then reliability against bit errors is improved, but circuit area and cost increase
Solution Approach 1:
The N separate check data values generated by the parallel lane encoders are merged by the mask circuitry into a single C-bit check data output. This merging process combines the error protection capabilities of all N lanes into a unified check data structure, providing comprehensive error resilience while using shared mask circuitry rather than duplicating full encoder logic for each lane.
Solution Approach 2:
The mask circuitry serves multiple functions: it combines the N check data values from different lanes, applies appropriate masking to generate the final C-bit check data, and handles various data ordering scenarios. This multi-functional design reduces the need for separate dedicated circuits for each function, thereby reducing overall circuit area.
Data Source
AI summary
An encoder for generating check data to accompaning payload data uses parallel lane encoders each using a common encoder matrix. Mask circuitry applies mask values to the lane check data generated by the lane encoders. The mask circuitry generates check data for the K-bits of payload data. The mask values applied by the mask circuitry may be selected so as to bring about a re-ordering of the M-bit words.