Parallel Latch Scan Chain Initialization for Electronic Circuits
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Solution Overview
Problem
Existing electronic circuits face challenges in rapidly initializing or reinitializing systems or core processors during power-on or deep power management states, particularly in complex systems where customization is required due to faulty designs or different applications, leading to increased initialization time and power consumption.
Innovation Solution
The implementation of latch scan chains with a built-in test structure that generates and feeds scan-in data in parallel to initialize the electronic circuit, utilizing existing test registers and pseudo-random pattern generators to achieve fast and customizable initialization, reducing the need for additional hardware and logic overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional serial scan methods are used for initialization, then the circuit structure remains simple, but the initialization time increases significantly with system size
Solution Approach 1:
The scan chains are divided into multiple parallel segments, each initialized independently. This segmentation allows simultaneous initialization of multiple chain segments, reducing total initialization time from O(n) serial operations to O(n/p) parallel operations where p is the number of parallel chains.
Solution Approach 2:
The existing test logic and scan chain infrastructure are reused for dual purposes: both testing and initialization operations. This multi-functionality eliminates the need for separate initialization hardware, achieving fast initialization without increasing device complexity.
2Productivity
If parallel initialization is implemented, then initialization speed improves, but hardware overhead increases
Solution Approach 1:
The scan chain infrastructure serves dual functions as both test vectors and initialization data pathways. By reusing existing test logic, multiplexers, and scan chain structures for initialization purposes, the patent achieves parallel initialization capability without adding dedicated initialization hardware, thus avoiding increased hardware overhead.
Solution Approach 2:
The initialization process leverages the circuit's own existing test infrastructure to perform self-initialization. The scan chains and test logic that are already present in the design are repurposed to load initialization patterns, eliminating the need for external or additional initialization hardware.
3Adaptability or versatility
If custom initialization is implemented for different applications, then adaptability improves, but initialization complexity increases
Solution Approach 1:
Application-specific initialization patterns are pre-computed and stored in lookup tables or pattern memory before runtime. During initialization, these pre-prepared patterns are simply loaded into the scan chains, avoiding complex real-time generation logic and reducing initialization complexity while maintaining adaptability to different applications.
Solution Approach 2:
Different applications are accommodated by changing the initialization pattern parameters (data values, scan chain selection, clock cycles) rather than changing the underlying initialization architecture. This parameter-based configuration allows custom initialization for different applications without increasing structural complexity.
Data Source
AI summary
The invention relates to an electronic circuit (10) having one or more latch scan chains (12), the electronic circuit (10) comprising (i) a built-in test structure (14); (ii) generation means (16) for simultaneously generating scan-in data for each of said scan chains (12); (iii) interception means (18) for simultaneously intercepting test lines (20) of said scan chains (12), said test lines (20) comprising scan-in lines (22) and/or control lines (24). Said interception means (18) are responsive to said generation means (16) in order to simultaneously feed the generated scan-in data into each of said scan chains (12) for initializing the electronic circuit (10). The invention further relates to a method for initializing an electronic circuit (10), as well as a data processing system (210) for initializing an electronic circuit (10).