Parallel LDPC Decoding with Demapping and Bit Deinterleaving
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing LDPC decoder configuration on the reception side lacks parallel processing in the demapper and bit deinterleaver stages, leading to bottlenecks that delay the restoration of LDPC codes, particularly in systems like DVB-T.2 using the 64K16QAM system.
Innovation Solution
A data processing apparatus and method that include parallel demapping, bit interleave reverse processing, and LDPC decoding portions, enabling parallel processing of LDPC codes with a predetermined bit width, such as 360 bits, to efficiently decode LDPC codes by executing demapping and bit interleave reverse processing in parallel, thereby bypassing previous bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If serial processing is used in the demapper and bit deinterleaver, then the device complexity is reduced, but the processing speed becomes a bottleneck and delays LDPC code restoration
Solution Approach 1:
The demapper is divided into multiple parallel demapping units (first demapping unit, second demapping unit, etc.), each processing a specific portion of the data stream simultaneously. This segmentation enables parallel processing while maintaining manageable complexity for each individual unit.
Solution Approach 2:
The processing architecture transitions from a single-dimensional serial processing flow to a multi-dimensional parallel structure by introducing multiple demapping units operating simultaneously on different data segments, effectively adding a parallel processing dimension to the system.
2Productivity
If parallel processing is implemented in the demapper and bit deinterleaver, then the processing speed increases, but the device complexity increases
Solution Approach 1:
The data stream is segmented into multiple portions that can be processed in parallel by separate demapping units. Each unit handles a specific segment, enabling high throughput while keeping each processing unit's complexity manageable through division of labor.
Solution Approach 2:
Multiple demapping units are designed with identical or similar functional structures, allowing them to perform the same demapping operation on different data segments. This universality simplifies the overall system design while achieving high parallel processing throughput.
3Adaptability or versatility
If bit interleave processing is executed only for robustness dispersion, then the processing simplicity is maintained, but the compatibility with parallel processing in LDPC decoder is reduced
Solution Approach 1:
The bit interleave processing is designed with specific local characteristics that match the parallel processing requirements of the LDPC decoder. By optimizing the interleave pattern for parallel processing compatibility rather than just robustness dispersion, the system achieves better adaptability without excessive complexity.
Data Source
AI summary
A data processing apparatus and method with efficient decoding of an LDPC code under bit interleave processing is disclosed. In one example, a data processing apparatus includes a parallel demapping portion configured to obtain a second data stream by executing in parallel demapping processing corresponding to mapping on a transmission side for a first data stream as an object of processing. The apparatus also includes a bit interleave reverse processing portion configured to obtain a third data stream by executing in parallel bit interleave reverse processing corresponding to bit interleave on the transmission side for the second data stream, and an LDPC decoding portion configured to decode the third data stream which is inputted in parallel with a bit group as a unit. The present disclosure, for example, can be applied to a receiving apparatus for a digital broadcasting.