Parallel LDPC Decoder Architecture for High-Throughput Low-Power Decoding
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Solution Overview
Problem
Designing high-throughput, low-power LDPC decoder architectures for gigabit wireless communication systems is challenging due to the need for efficient error control schemes that can handle varying data rates and power consumption constraints.
Innovation Solution
The proposed solution involves an LDPC decoder apparatus and method that uses a lifting factor to extend the base LDPC code length, applying pre-shift, relative-shift, and post-shift values within a decoding loop, and iteratively processing layers of the LDPC code using multiple processing elements to achieve efficient decoding while reducing hardware complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple LDPC processing elements are used to decode separate portions of the LDPC codeword in parallel, then decoding throughput is improved, but hardware complexity increases
Solution Approach 1:
The LDPC codeword is divided into multiple portions, with each portion decoded by a separate processing element. The codeword length is extended using a lifting factor to create a structured format that enables this segmentation while maintaining decoding efficiency
Solution Approach 2:
Multiple processing elements are designed with identical or similar architectures, each capable of decoding a portion of the codeword. This universal design allows the system to scale throughput by adding more processing elements without increasing the complexity of each individual element
2Reliability
If code length is extended using lifting factor, then error performance is improved, but decoding complexity increases
Solution Approach 1:
The extended codeword from lifting is segmented into multiple portions that can be processed in parallel. This segmentation reduces the computational burden on each processing element while maintaining the error performance benefits of the longer code length
Solution Approach 2:
The lifting factor extends the code in a structured dimensional framework, creating a base LDPC code length that is multiplied by the lifting factor. This dimensional extension allows systematic segmentation and parallel processing
3Adaptability or versatility
If more processing elements are deployed to handle varying data rates, then adaptability is improved, but power consumption increases
Solution Approach 1:
The system dynamically activates or deactivates processing elements based on the required data rate. When lower throughput is needed, fewer processing elements are active, reducing power consumption while maintaining the capability to handle higher data rates when required
Solution Approach 2:
Each processing element is designed to be multi-functional, capable of handling different portions of the codeword at different data rates. This universality allows the system to adapt to varying data rate requirements using the same hardware resources
Data Source
AI summary
An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.