Parallel LDPC Decoder Layout for Contention-Free Multimode Processing
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Solution Overview
Problem
Current wireless communication systems face challenges in efficiently decoding low-density parity-check (LDPC) codes due to complex processing requirements and high decoding complexity, which affects data transmission reliability and efficiency.
Innovation Solution
A receiver and decoder system is developed, featuring multiple memory units and unit decoders with processor arrays that perform parallel low-density parity-check decoding operations using a decoding matrix, allowing independent and coordinated decoding of received data to reduce complexity and enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel decoding operations are implemented, then decoding efficiency is improved, but device complexity increases
Solution Approach 1:
The decoding operation is segmented into multiple independent unit decoders, each handling a specific portion of the received data and a specific portion of the decoding matrix. This segmentation enables parallel processing while keeping each unit's internal structure relatively simple, thus improving decoding efficiency without excessively increasing overall device complexity.
Solution Approach 2:
Each unit decoder is designed with universal functionality to perform low-density parity-check decoding operations. The unit decoders use the same decoding algorithm and structure, but operate on different data portions simultaneously. This multi-functionality approach allows the system to achieve parallel processing capability while maintaining uniform and manageable device complexity across all units.
2Device complexity
If multiple unit decoders operate independently, then decoding complexity is reduced, but coordination between decoders becomes more difficult
Solution Approach 1:
The decoding matrix is divided into multiple portions, with each unit decoder assigned to process a specific portion. This segmentation ensures that each decoder operates independently on its assigned data and matrix portion, reducing the complexity of individual decoding operations. The independent operation simplifies the control logic for each unit while the overall system coordination is achieved through the predefined segmentation scheme.
3Productivity
If LDPC codes are used to achieve high data transmission rates, then transmission efficiency is improved, but processing complexity increases
Solution Approach 1:
The received data is divided into multiple portions that are processed in parallel by different unit decoders. Each unit decoder processes a smaller portion of the data using LDPC decoding, which reduces the processing complexity for each individual unit compared to processing the entire data stream sequentially. This segmentation enables the system to achieve high data transmission rates using LDPC codes while keeping the processing complexity manageable through parallel distribution.
Solution Approach 2:
The patent creates a controlled parallel processing environment where multiple unit decoders operate simultaneously with predetermined data assignments. This structured environment allows LDPC codes to be effectively implemented at high transmission rates by distributing the processing load across multiple independent units, each operating in a simplified computational context that reduces overall processing complexity.
Data Source
AI summary
A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas for receiving data; a plurality of memory units for storing the received data; and a number of decoders configured to perform a Low Density Parity Check (LDPC) decoding operation. Each of the decoders further is configured to independently decode at least a portion of the received data using a portion of a decoding matrix. Each of the number of decoders coordinates the low density parity check decoding operation with other decoders. The decoders can use a parallel process, a pipeline process or a combination of a parallel and pipeline process.