Parallel LDPC Encoding With Overlapped Interleaving and Parity Coding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing high bit rate digital communications systems using serially concatenated LDPC codes face limitations in encoding and decoding bit rates due to latency introduced by their serial architecture, which restricts performance and inefficient use of hardware resources.
Innovation Solution
A method that parallelizes the interleaving and parity coding steps by starting the parity coding after a predetermined number of bits, allowing these steps to be performed concurrently without waiting for the completion of the interleaving step, using a quasi-cyclic parity check matrix with identity sub-matrices to optimize resource utilization and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial architecture is used for encoding and decoding, then hardware resource utilization is improved, but encoding and decoding bit rate are limited due to latency
Solution Approach 1:
The patent segments the encoding process into multiple independent coding units that can be processed in parallel. Specifically, the input data is divided into several blocks, and multiple coding operations are performed simultaneously on different blocks using separate coding units, thereby increasing the overall encoding throughput without requiring a complete architectural redesign.
Solution Approach 2:
The patent transitions from a single-dimensional serial processing architecture to a multi-dimensional parallel architecture by introducing multiple coding units operating simultaneously. This dimensional expansion allows the system to process multiple data blocks concurrently, effectively increasing the encoding bit rate while maintaining efficient hardware utilization.
2Productivity
If parallel processing is implemented to increase bit rate, then encoding and decoding speed is improved, but device complexity increases
Solution Approach 1:
The patent designs coding units that can be configured to perform multiple coding functions. Each coding unit is capable of handling different coding schemes and can be dynamically allocated to different data blocks, reducing the need for dedicated hardware for each coding operation and thereby limiting the increase in device complexity.
Solution Approach 2:
The patent performs preliminary organization and preparation of input data into standardized blocks before parallel processing begins. This pre-processing step ensures that data is ready for immediate parallel encoding, minimizing setup overhead and allowing the parallel processing units to operate at full efficiency without excessive complexity.
3Reliability
If serial concatenated coding is used, then error correction performance is improved, but latency increases due to sequential processing
Solution Approach 1:
The patent segments the concatenated coding process into parallelizable stages, where different coding operations can be performed simultaneously on different data blocks. This segmentation maintains the error correction benefits of serial concatenated coding while reducing the overall latency by eliminating sequential bottlenecks.
Solution Approach 2:
The patent ensures continuous processing by overlapping the execution of different coding stages across multiple data blocks. While one block is being processed by the outer code, another block can be processed by the inner code, maintaining continuous useful action and reducing idle time that contributes to latency.
Data Source
AI summary
A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).