Parallel LFSR Encoding for High-Clock BCH Code Generation
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Solution Overview
Problem
Existing Linear Feedback Shift Registers (LFSRs) face challenges in achieving high-frequency operations while maintaining generality, particularly when handling multiple bits in parallel, as the increased shifts required lead to lower clock frequencies and more complex logic, which complicates the encoding process.
Innovation Solution
The method involves splitting a bit stream into multiple streams, encoding each stream in parallel using multiple LFSRs, merging these streams while bypassing feedback circuits of some LFSRs, and shifting the combined stream through the LFSRs, allowing for efficient encoding without compromising clock frequency or generality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bits are processed in parallel to increase encoding speed, then productivity is improved, but device complexity increases and clock frequency decreases
Solution Approach 1:
The patent divides the bit stream into multiple separate streams and processes them through multiple independent LFSR instances in parallel. Each LFSR handles a portion of the encoding task independently, allowing the system to achieve higher overall encoding throughput without requiring complex inter-stage logic within a single LFSR. This segmentation resolves the contradiction by distributing the encoding workload across multiple simpler units rather than complicating a single unit.
2Productivity
If multiple bits are processed in parallel to increase encoding speed, then productivity is improved, but clock frequency decreases
Solution Approach 1:
The patent merges the outputs of multiple parallel LFSR encodings into a single combined stream. By processing multiple bit streams in parallel through separate LFSRs and then combining their results, the system achieves high productivity while each individual LFSR operates at its full clock frequency without the frequency degradation that would result from complex multi-stage logic.
3Adaptability or versatility
If programmable taps are added to support configurable BCH codes, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements programmable tap configurations that can be dynamically adjusted to support different BCH code requirements. The LFSR structure includes configurable elements that allow the feedback polynomial to be changed based on the specific error correction code being implemented. This dynamic configurability provides adaptability for various code standards while maintaining a relatively simple base LFSR structure that can be reconfigured rather than redesigned for each code type.
Data Source
AI summary
An encoder and a method for encoding a first stream of bits, the method may include splitting the first stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift registers (LFSRs), the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR of the multiple LFSRs; wherein the encoding comprises feeding the multiple second streams to the multiple LFSRs; merging the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSRs; and encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSRs while bypassing feedback circuits of some of the multiple LFSRs; and shifting the fourth stream through the multiple LFSRs.