Parallel LFSR Architecture for High-Throughput Output Generation
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Solution Overview
Problem
Existing linear feedback shift registers (LFSRs) face limitations in operating at high speeds when implemented in slower technologies due to individual flip flops being limited by setup time.
Innovation Solution
A parallelized design for LFSRs is introduced, utilizing P parallel chains of flip flops clocked by a slow clock derived from a fast clock divided by P, with a multiplexer and exclusive-OR circuits to generate N-bit output words at each pulse of the fast clock, enabling higher throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional single-chain LFSR design is used, then device complexity is low, but operating speed is limited by flip flop setup time
Solution Approach 1:
The LFSR is divided into P parallel chains of flip flops, each chain processing a subset of the N bits. This segmentation allows each chain to operate independently at lower speeds while the overall system achieves higher throughput by processing multiple bits in parallel across the chains.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing chain to a multi-dimensional parallel structure by introducing P parallel chains that operate simultaneously. This dimensional expansion from 1D to PD processing enables the system to overcome the speed limitations of individual flip flops.
2Productivity
If parallel chains are introduced to increase speed, then throughput increases, but device complexity increases
Solution Approach 1:
The outputs from P parallel chains are merged through a multiplexer that selects and combines the results from different chains. This merging approach allows the system to maintain high throughput by processing data through multiple paths while consolidating the outputs to maintain the expected LFSR sequence properties.
Solution Approach 2:
A multiplexer acts as an intermediary component that receives inputs from P parallel chains and selectively passes the appropriate output based on the current chain identifier. This intermediary enables the parallel chains to contribute to the overall throughput without requiring complex direct interconnections between all chains.
3Speed
If fast clock is used to achieve high speed, then operating frequency increases, but setup time requirements become more stringent
Solution Approach 1:
The system uses a fast clock that operates at P times the frequency of the slow clock, but each parallel chain only updates its state every P clock cycles. This periodic action allows the fast clock to provide the necessary timing resolution while the chains update at a slower, more relaxed rate that satisfies setup time requirements.
Solution Approach 2:
The parallel chains perform their state transitions in advance during their designated update cycles, preparing the data for the fast clock's sampling points. This preliminary action ensures that all data is ready and stable before the fast clock captures it, meeting setup time requirements while maintaining high operating frequency.
Data Source
AI summary
An N-bit linear feedback shift register includes P parallel chains of flip flops each having an input and output. The input is coupled to output of an XOR circuit for that parallel chain. Inputs of the XOR circuit for that parallel chain are coupled to outputs of different flip flops of the P parallel chains according to exponents of a primitive polynomial of order N−1. The flip flops of the P parallel chains of flip flops are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are respectively produced from the outputs of last flip flops of each of P parallel chains of flip flops. Readout circuitry clocked by a first clock having a frequency that is P times that of the first clock passes a different one of the P pre-LFSR outputs at each clock cycle as a LFSR output.