Parallel Load Store Cache Merging for Latency Reduction
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Solution Overview
Problem
Conventional approaches to accommodating multiple accesses in caches result in unsatisfactory latency penalties due to the need for additional banks, ports, and arbitration, which delay access to data and trigger critical Load Hit signals.
Innovation Solution
The method involves accessing a block of the load cache and its logically and physically paired block in a store coalescing cache in parallel, merging data on a per-byte basis, and providing access to the merged data, allowing for quicker access to multiple loads and stores by executing block access arbitrations and tag identification in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multi-ported caches or caches with multiple tag and data banks are used to accommodate multiple accesses in a single cycle, then throughput is improved, but latency penalties increase due to serial arbitrations and additional access time
Solution Approach 1:
The cache is segmented into multiple independent banks (first bank, second bank, third bank, fourth bank), each capable of handling requests independently. This segmentation allows parallel access to different cache banks, eliminating the need for serial arbitrations and reducing latency while maintaining high throughput.
Solution Approach 2:
Multiple cache banks are merged into a unified cache structure that can serve multiple requests simultaneously. The unified cache combines the capabilities of separate banks while enabling parallel operations, thus improving throughput without incurring latency penalties from serial arbitration.
2Productivity
If additional banks and ports are added to accommodate high throughput requests, then productivity is improved, but device complexity increases
Solution Approach 1:
Each cache bank is designed with multi-functionality, capable of handling both load and store requests independently. This universal design allows the cache system to accommodate high throughput requests without requiring specialized structures for different request types, thereby reducing overall device complexity.
Solution Approach 2:
The cache structure transitions from a single-dimension sequential access model to a multi-dimensional parallel access model. By organizing cache banks in a way that enables simultaneous access from multiple ports, the system achieves high throughput without proportionally increasing structural complexity.
Data Source
AI summary
Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.