Parallel Logic Core Checking for Unannounced Failure Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing safety-critical systems, such as nuclear plant reactor protection systems, face challenges in ensuring high integrity and reliability due to unannounced failures in logic circuits, which can go undetected for extended periods, and are vulnerable to common-mode failures in software-microprocessor systems, leading to potential catastrophic effects.
Innovation Solution
The implementation of parallel logic circuit cores with a redundancy checker to detect failures by comparing parallel paths for equivalence and a built-in self-test engine to periodically exercise individual paths, ensuring unannounced failures are exposed without disrupting ongoing processes, combined with hardware-based logic devices to avoid software dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based systems are used for safety-critical control, then system flexibility and programmability are improved, but reliability deteriorates due to common-mode failures and unannounced errors
Solution Approach 1:
The patent replaces software-based control systems with hardware-based logic circuits implemented in FPGA or ASIC. This substitution eliminates the inherent unreliability of software while maintaining functional capability through dedicated hardware logic that performs safety functions without executables, thereby resolving the contradiction between flexibility and reliability.
Solution Approach 2:
The patent implements parallel redundant logic circuits where multiple copies of the same safety function are executed simultaneously in parallel. These parallel paths are then voted on to determine the final output, ensuring that if one path fails due to unannounced errors, the system can still operate correctly through the majority vote, thus improving reliability while maintaining functional adaptability.
2Reliability
If parallel redundant logic circuits are implemented, then fault tolerance is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple parallel redundant logic circuits into a single integrated hardware implementation using FPGA or ASIC technology. By combining the redundant paths and voting logic into one unified device, the system achieves fault tolerance without proportionally increasing external system complexity, as the redundancy is embedded within the logic device itself.
Solution Approach 2:
The patent designs the parallel redundant logic circuits to perform multiple functions: normal safety monitoring, self-diagnosis, and failure mitigation all within the same hardware structure. The voting circuit serves both to determine the correct output and to detect failures, reducing the need for separate dedicated components and thereby limiting complexity growth.
3Reliability
If self-test circuits are added to detect unannounced failures, then reliability is improved, but device complexity and maintenance requirements increase
Solution Approach 1:
The patent implements self-test circuits that automatically diagnose and report failures within the logic device without requiring external testing equipment or intervention. The system performs self-diagnosis during normal operation or idle periods, identifying unannounced failures and generating diagnostic information that simplifies maintenance by eliminating the need for complex external testing procedures.
Solution Approach 2:
The patent incorporates self-test functionality that can be activated during idle periods or scheduled maintenance windows to perform preliminary detection of potential failures before they affect system operation. This allows the system to identify and report issues in advance, reducing the complexity of maintenance by enabling proactive rather than reactive repair approaches.
Data Source
AI summary
The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.