Parallel Differential Logic Gates for Low-Voltage Multi-Input Design
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Solution Overview
Problem
Existing differential emitter coupled logic architectures require significant voltage headroom due to multiple transistor and resistor voltage drops, limiting the number of inputs that can be handled and necessitating higher voltage power supplies, which is disadvantageous in many design situations.
Innovation Solution
The implementation of a logic device architecture where the collectors of transistors in differential pairs are coupled to an upper voltage via resistors of different resistive values, allowing for the creation of AND or OR gates with a single offset level, eliminating the need for stacked devices and enabling operation at lower supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked differential input pairs are used to increase the number of inputs, then the number of inputs is increased, but the voltage headroom required increases due to additional transistor and resistor voltage drops
Solution Approach 1:
The patent divides the logic gate into separate parallel differential input pairs instead of stacking them vertically. Each differential pair operates independently with its own current source, eliminating the need for multiple transistors and resistors in series. This segmentation maintains the number of inputs while reducing the voltage headroom requirement to a single transistor voltage drop plus resistor drop, rather than cumulative drops from stacked devices.
2Quantity of substance
If stacked differential input pairs are used to increase the number of inputs, then the number of inputs is increased, but higher voltage power supplies are necessitated
Solution Approach 1:
By segmenting the logic gate into parallel differential pairs, each with independent current sources, the patent eliminates the cumulative voltage drops that would require higher power supply voltages. The power supply voltage requirement is reduced to accommodate only a single transistor voltage drop and resistor drop, enabling the implementation of multi-input gates without increasing the power supply voltage.
3Adaptability or versatility
If two sets of differential outputs are provided at different offset levels, then the logic gate can drive different stages, but the device complexity increases
Solution Approach 1:
The patent merges the output functionality by providing a single set of differential outputs that can drive subsequent logic stages. The parallel differential input pair architecture naturally produces outputs at a unified offset level, eliminating the need for separate output sets at different offset levels. This reduces device complexity while maintaining the ability to drive different logic stages through the single unified output interface.
Data Source
AI summary
Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.