Parallel Logic Simulation Scheduling via Input Change Detection
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Solution Overview
Problem
Current parallel logic simulation techniques face scalability issues and inefficiencies, particularly with synchronization costs increasing beyond a few processors, and uneven work distribution, leading to performance bottlenecks in complex multi-core computing systems.
Innovation Solution
The approach involves dynamically scheduling the simulation of electronic circuit designs by computing the influence of input changes across regions, focusing on parallel execution of logic levels with input changes, and using aggregated blocks to optimize computation and memory access, thereby avoiding redundant evaluations and minimizing synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel event driven simulation is used to increase simulation performance, then simulation speed is improved, but synchronization cost increases significantly beyond four or eight processors
Solution Approach 1:
The circuit design is divided into multiple regions that are simulated in parallel, with each region processed by a separate processor. This segmentation allows the simulation to scale beyond a fixed number of processors by organizing work into manageable regional units that can be distributed across available computational resources.
Solution Approach 2:
The simulation uses dynamic scheduling where processors are assigned regions based on current workload and input changes rather than static partitioning. This dynamic approach allows the system to adapt to varying computational demands and scale efficiently with the number of available processors, avoiding the synchronization bottlenecks of static parallel approaches.
2Productivity
If parallel event driven simulation is used to evaluate only changed components, then computation is limited to necessary parts, but work distribution becomes uneven among processors
Solution Approach 1:
The system monitors input changes and dynamically adjusts processor assignments based on which regions have changed. This feedback mechanism ensures that processors are allocated to regions with actual computational work, preventing idle processors while maintaining efficient evaluation of only changed components. The workload distribution automatically balances as the system responds to changing simulation conditions.
3Reliability
If parallel oblivious simulation is used to simplify computation by evaluating all components, then work starvation is eliminated, but redundant computation increases simulation time
Solution Approach 1:
The system applies different evaluation strategies to different regions based on their characteristics and input change status. Regions with input changes receive detailed event-driven evaluation, while regions without changes are skipped entirely. This local differentiation eliminates redundant computation in stable regions while maintaining computational completeness in changed regions, achieving both efficiency and reliability.
Data Source
AI summary
An approach for simulating an electronic circuit design uses the influence of a set of input changes of regions of the circuit design to schedule which levels within regions of a circuit should be simulated. The state of one or more inputs of one or more regions of the circuit design is checked to determine if inputs to these regions changed. For each input having an input change, a logic level depth associated with the input is computed. Using the computed logic levels, a maximum logic level depth of the one or more regions is computed for a set of input changes. Thus, for each region that has an input with a state indicating an input change, simulation may be scheduled for first logic level through and including the determined maximum logic level in each region of the circuit design in parallel.