Parallel Linear Sequential Circuit Computation via Pre-computed Matrices
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Solution Overview
Problem
Existing linear sequential circuits are inadequate for high-speed wireless communication systems due to their limited computational speed, requiring multiple cycles for each bit transition and lacking efficient processing capabilities in traditional processors.
Innovation Solution
A method and system for parallel computation of linear sequential circuits using pre-computed multistep state transition and output generation matrices, enabling multiple state transitions and output bits to be generated in a single clock cycle through dot product operations, specifically utilizing Galois field dot products and efficient implementation in processor registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional shift register implementation is used, then the circuit structure is simple, but the computational speed is limited to one bit per clock cycle
Solution Approach 1:
The patent segments the linear sequential circuit computation into multiple parallel paths by decomposing the state transition into multiple clock cycles. Each path processes a portion of the state bits in parallel, allowing multiple bits to be computed simultaneously rather than sequentially, thus achieving high-speed computation while maintaining a manageable circuit structure.
Solution Approach 2:
The patent transitions from a single-clock-cycle sequential processing approach to a multi-clock-cycle parallel processing approach. By distributing the computation across multiple time dimensions (clock cycles), the system achieves high computational throughput without requiring an exponentially complex circuit structure, effectively trading time for space complexity.
2Productivity
If look-up table approach is used, then computation speed is modestly improved, but the table size increases exponentially limiting further speedup
Solution Approach 1:
Instead of using a single large look-up table that would require exponential size, the patent segments the state space into smaller subsets that can be processed in parallel across multiple clock cycles. Each cycle processes a portion of the state transitions using smaller, more manageable tables or direct logic, avoiding the exponential memory requirement while achieving high-speed computation.
Solution Approach 2:
The patent pre-computes and stores the multistep state transition matrix and output generation matrix offline. These pre-computed matrices are then used during operation to directly determine the next state and output bits without requiring real-time computation or large look-up tables, achieving high-speed operation with minimal memory requirements.
3Productivity
If traditional processor/DSP is used, then flexibility is maintained, but each bit requires shifting, masking and manipulation operations reducing speed
Solution Approach 1:
The patent replaces the mechanical bit-by-bit manipulation operations (shifting, masking, XOR) with direct matrix multiplication operations. Instead of sequentially processing each bit through multiple instruction cycles, the system uses parallel matrix-vector multiplication to compute all next state bits and output bits simultaneously, dramatically reducing the number of operations required.
Solution Approach 2:
The patent changes the computational parameters by using Galois Field (GF(2)) arithmetic instead of standard binary arithmetic. This parameter change allows the use of optimized matrix multiplication algorithms and enables parallel processing of multiple bits simultaneously, achieving high-speed computation while simplifying the operational complexity through mathematical properties of GF(2).
Data Source
AI summary
A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and the multiple output bits can be computed by multiplying the current input-state vector with a multistep next state transition matrix and a multistep output generation matrix, respectively. Multiple state transitions and multiple output bits can be generated in parallel in a single clock cycle based on the pre-computed state transition matrix and the output generation matrix utilizing a dot product in order to improve computational speed. Such a simple augmentation provides a flexible and inexpensive solution for high speedup linear sequential circuit computation with respect to a processor.