Parallel LUT Reads for Random SIMD Data Access
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Solution Overview
Problem
Random read accesses within a block of data are difficult to parallelize for vector SIMD operations, leading to performance bottlenecks in algorithms like BRIEF, ORB, FAST feature detectors, and CoHOG, as existing vector load instructions cannot efficiently handle non-sequential data access patterns.
Innovation Solution
Implementing plural parallel look-up tables to store data from main memory and using a look-up table read instruction for simultaneous data movement to a vector destination register, enabling vector SIMD operations by partitioning memory into data cache and directly addressable memory with look-up tables stored in the latter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vector load instructions are used to fetch data, then sequential data access is efficient, but random read access to non-sequential locations cannot be parallelized
Solution Approach 1:
The patent introduces look-up tables as an intermediary data structure between main memory and the vector processing unit. These tables store pre-computed addresses or data mappings that enable random read access patterns to be converted into sequential or predictable access patterns, which can then be efficiently handled by vector load instructions. The look-up tables act as a mediator that transforms complex random access requirements into forms suitable for vectorized processing.
Solution Approach 2:
The patent employs preliminary action by pre-loading data into look-up tables before the main vector processing operation. The data is first fetched from main memory and stored in the look-up tables in advance, allowing the vector processing unit to perform parallel read operations on the pre-organized data without needing to handle complex random access patterns during the critical processing phase.
2Productivity
If scalar loads are used for random access, then data can be fetched from any location, but processing speed drops drastically compared to vector operations
Solution Approach 1:
The patent applies segmentation by dividing the data access operation into two distinct phases: (1) data loading phase where data is fetched from main memory and stored in look-up tables using flexible random access, and (2) processing phase where vector operations perform parallel reads from the segmented table structures. This segmentation allows each phase to optimize for its specific requirement - flexibility during loading and speed during processing.
Solution Approach 2:
The patent transitions from one-dimensional sequential vector loading to a two-dimensional approach by introducing look-up tables that map random access patterns into a structured format. The look-up tables add an addressing dimension that enables random access semantics while maintaining the sequential access benefits for vector operations, effectively adding an indirect addressing layer between the processor and main memory.
3Productivity
If look-up tables are implemented for random access, then parallel data fetching is enabled, but overhead of defining and managing tables increases
Solution Approach 1:
The patent designs the look-up table structure to serve multiple functions: it acts as a cache for frequently accessed data, provides address mapping for random access patterns, and enables vectorized loading operations. By making the table structure multi-functional, the patent reduces the need for separate mechanisms for each function, thereby managing complexity more efficiently while maintaining parallel data fetch capabilities.
Data Source
AI summary
This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.