Parallel LZ4 Decompression Engine for Execution Stall Reduction

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing data decompression methods using lossless compression algorithms, such as LZ4, can cause execution stalls due to the variability in time required to copy large repeated sets of bytes, leading to inefficient processing and potential performance issues.

Innovation Solution

A parallel decompression engine with separate hardware paths for sequence processing and copying/replacement logic, implemented using special purpose integrated circuits or processor cores, processes compressed data sets to efficiently generate uncompressed data by handling literal and repeated bytes in parallel, mitigating execution stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If sequential decompression processing is used, then device complexity is reduced, but execution stalls occur due to variability in copying time

Engineering Contradiction:

Improvedecompression engine structureVSAvoidexecution stall likelihood

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The decompression engine is segmented into two independent hardware paths: a first hardware path for sequence processing (extracting literal bytes and offset/length information) and a second hardware path for copying and placement operations. This segmentation allows simultaneous execution of different decompression tasks, eliminating execution stalls while maintaining manageable device complexity through modular architecture.

Inventive Principle:

Principle #1Segmentation

2Reliability

If parallel hardware paths are used, then execution stall likelihood is reduced, but device complexity increases

Engineering Contradiction:

Improveexecution stall likelihoodVSAvoiddecompression engine structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Device complexity

If single-core processing is used, then device complexity is reduced, but processing efficiency decreases

Engineering Contradiction:

Improveprocessor configurationVSAvoiddecompression processing efficiency

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The processing functionality is segmented across multiple cores: sequence processing logic is implemented by a first hardware path (which can be a dedicated core or circuit), and copying/placement logic is implemented by a second hardware path (another dedicated core or circuit). This segmentation enables parallel execution, significantly improving decompression throughput without requiring a complex multi-core general-purpose processor.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A queue mechanism acts as an intermediary between the first hardware path and the second hardware path. The queue buffers offset/length information extracted by the first path, allowing the second path to consume data at its own pace. This intermediary decouples the two processing paths, enabling independent optimization of each while maintaining overall system efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Quantity of substance

If large repeated byte patterns are processed, then compression ratio is improved, but execution stalls increase

Engineering Contradiction:

Improvecompression ratioVSAvoidexecution stall likelihood

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first hardware path performs preliminary extraction of offset and length information for repeated byte patterns before the actual copying operation. By preparing the copy parameters in advance through the queue mechanism, the system ensures that when large repeated patterns need to be copied, the second hardware path can immediately execute the operation without stalling, thus maintaining high throughput even for highly compressible data.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9973210B1Reduction of execution stalls of LZ4 decompression via parallelization

Publication Date: 2018.05.15 EMC IP HLDG CO LLC

AI summary

A parallel decompression engine has separate hardware paths for sequence processing and repeated byte copying/placement. Literal byte extraction logic obtains literal bytes from a selected sequence. Literal byte write logic writes the obtained literal bytes into an uncompressed data set that is being generated. Offset and length extraction logic obtains the offset and length of repeated bytes from the selected sequence. In a separate hardware path, copying and placement logic uses the offset and length to find and copy the length of repeated bytes at the specified offset in the uncompressed data set, and place the copied repeated bytes back into the uncompressed data set adjacent to the literal bytes.