Hierarchical Parallel Machines Using Aggregated FSM State Vectors
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Solution Overview
Problem
Hierarchical parallel machines face challenges in reducing data processing time due to the large amount of state information passed between finite state machine engines, which limits real-time operation and increases processing delays.
Innovation Solution
Implementing a hierarchical structure with cascaded finite state machine engines, where each engine processes and outputs data to the next, allowing for real-time operation and reducing the need to pass extensive state information by using compressed or aggregated data vectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If extensive state information is passed between finite state machine engines, then complete state information is available for processing, but data processing time increases and real-time operation is limited
Solution Approach 1:
The patent extracts and passes only the essential state information between finite state machine engines rather than complete state information. This selective extraction of critical state data reduces the volume of information transmitted while maintaining the ability to perform necessary processing operations, thereby reducing data processing time without completely losing essential state information.
Solution Approach 2:
The patent changes the parameters of state information by transforming detailed state data into compressed or aggregated state representations. This parameter transformation reduces the dimensionality and volume of state information that needs to be passed between engines, enabling faster processing while preserving the essential characteristics needed for pattern recognition and state transitions.
2Measurement precision
If extensive state information is passed between finite state machine engines, then accurate pattern recognition is maintained, but processing delays increase
Solution Approach 1:
The patent extracts only the critical state information necessary for accurate pattern recognition rather than passing complete state information. By identifying and transmitting only the essential state parameters that contribute to pattern recognition accuracy, the system maintains measurement precision while reducing processing delays.
Solution Approach 2:
The patent applies partial action by passing a subset of state information that is sufficient for accurate pattern recognition without transmitting the complete state data set. This partial information transmission achieves the necessary recognition accuracy while minimizing processing time and delays.
3Loss of time
If compressed or aggregated data vectors are used, then data processing time is reduced, but device complexity increases
Solution Approach 1:
The patent segments the finite state machine system into a hierarchical structure with multiple levels of engines. Each engine processes and passes compressed state information to the next level, distributing the processing complexity across multiple components. This segmentation enables the use of compressed data vectors while managing device complexity through modular hierarchical organization.
Solution Approach 2:
The patent introduces a hierarchical dimension to the system architecture, organizing finite state machine engines in multiple levels. This dimensional change allows compressed or aggregated data vectors to be processed efficiently at each level, with the hierarchical structure providing a framework that manages the complexity of compression and aggregation operations.
Data Source
AI summary
Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.