Parallel MAP Channel Detection With Reduced Trellis Complexity
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Solution Overview
Problem
High-speed, low-power, high-performance soft-output channel detectors for disk drives are challenging due to the complexity and power requirements of existing MAP detectors, which are larger and more power-intensive than SOVA detectors, making them unsuitable for high-speed, low-cost implementations.
Innovation Solution
A channel detection system utilizing multiple parallel MAP detectors operating at a reduced rate, with each detector generating log-likelihood ratios for multiple bits, and employing different trellis structures for forward and backward detectors to reduce complexity and increase speed, while ensuring all bits are constrained to minimize soft-output magnitude and adaptability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a MAP detector is used to achieve high detection performance, then bit-error rate performance is improved, but chip area and power consumption increase
Solution Approach 1:
The MAP detector is segmented into multiple parallel detectors operating at reduced rate. Each detector processes a subset of bits, allowing the overall system to achieve high performance while each individual detector unit requires less area. The parallel structure distributes the computational burden across multiple simpler units.
Solution Approach 2:
The detector operates at variable rates using quarter-rate and half-rate implementations. By dynamically adjusting the operating rate and using different trellis structures for forward and backward detectors, the system optimizes between performance and area requirements based on specific application needs.
2Reliability
If a MAP detector is used to achieve high detection performance, then bit-error rate performance is improved, but power consumption increases
Solution Approach 1:
By dividing the MAP detection function across multiple parallel detectors operating at quarter-rate, each detector unit consumes less power individually. The segmented approach allows the system to achieve the required performance while distributing and reducing the overall power consumption burden.
Solution Approach 2:
The detector uses periodic processing at reduced clock rates (quarter-rate and half-rate operations). Instead of continuous high-speed operation, the system processes data in periodic cycles at lower rates, significantly reducing dynamic power consumption while maintaining detection accuracy through the parallel structure.
3Productivity
If the detection rate is increased to achieve high throughput, then productivity is improved, but complexity and power consumption increase
Solution Approach 1:
The high-throughput requirement is met by segmenting the detection function into multiple parallel detectors. Each detector operates at a lower quarter-rate or half-rate, keeping individual complexity manageable, while the parallel combination achieves the required overall throughput without any single detector becoming overly complex.
Solution Approach 2:
Instead of increasing the clock rate of a single detector to improve throughput, the system adds parallelism in the temporal dimension by using multiple detectors operating at reduced rates. This dimensional shift from speed to parallel count allows high throughput without proportionally increasing the complexity of each detector unit.
Data Source
AI summary
Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.