Parallel Memory Access Control for Bandwidth Flexibility
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Solution Overview
Problem
Existing memory access technologies face limitations in bandwidth due to the fixed data width of memory modules, which restricts the amount of data that can be accessed per period, and increasing the data width to improve bandwidth reduces access flexibility.
Innovation Solution
A method and apparatus for controlling memory access that includes an access instruction with a parallel control field, a module address field, and an in-module address field, allowing flexible access to multiple memory modules, either continuously or discontinuously, to enhance bandwidth and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data width of memory module is increased to improve bandwidth, then the amount of data accessed per period is improved, but the flexibility of access decreases
Solution Approach 1:
The memory system is segmented into multiple memory modules (e.g., 16 modules), each with its own data width (32 bits or 64 bits). Instead of using a single large-width module, the system divides the memory into smaller independent modules that can be selectively accessed. This allows the processor to access multiple modules in parallel to achieve high bandwidth while maintaining the flexibility to access individual modules as needed.
Solution Approach 2:
The system dynamically selects which memory modules to access based on the access requirements. The access control logic can flexibly configure the number and combination of memory modules accessed in each operation, adapting to different bandwidth and flexibility requirements. This dynamic configuration resolves the contradiction by allowing the system to optimize for either bandwidth or flexibility depending on the specific access pattern.
2Adaptability or versatility
If the access data width is set to match the memory module data width, then the flexibility of each memory module access is improved, but the bandwidth is limited
Solution Approach 1:
The system merges multiple memory modules into a unified memory space that can be accessed simultaneously. By combining the capacity of multiple 32-bit or 64-bit modules, the system achieves effective bandwidth greater than any single module width while maintaining flexible access to individual modules. The access control logic can merge results from multiple modules to fulfill larger data transfer requirements.
Solution Approach 2:
Instead of increasing the data width in one dimension (which would reduce flexibility), the system adds another dimension by accessing multiple memory modules in parallel. This multi-dimensional approach allows the system to achieve high bandwidth through parallel access to multiple narrower modules, rather than using a single wide module, thereby resolving the contradiction between bandwidth and flexibility.
3Productivity
If multiple memory modules are accessed in parallel to increase bandwidth, then the amount of data accessed per period is improved, but the access control complexity increases
Solution Approach 1:
The access control logic is designed with multi-functionality to handle various access patterns uniformly. A single control unit can manage access to one or multiple memory modules based on configuration parameters, rather than requiring separate control logic for each access mode. This universal control approach reduces complexity while enabling parallel access to multiple modules for high bandwidth operations.
Data Source
AI summary
A method, an apparatus, and an electronic device for controlling memory access are disclosed. According to an embodiment, there is provided a method for controlling access to a memory including a plurality of memory modules configured in parallel. The method comprises: receiving an access instruction including an addressing field which comprise a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an addresses within a memory module; parsing the access instructions to determine the parallel control field, the module address field and the in-module address field; determining one or more memory modules to be accessed based on the parallel control field and the module address field; and accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field.