Parallel Memory Cell Access in Cross-Point Arrays

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Solution Overview

Problem

Existing methods for accessing multiple memory cells in a cross-point array are inefficient due to the need for sequential access operations, limiting bandwidth and scalability in devices using threshold-switching phase change memory cells.

Innovation Solution

A method is developed to simultaneously access multiple memory cells in parallel by thresholding and accessing them using reduced bias voltages, allowing for concurrent write, erase, and read operations, which increases access bandwidth and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential access operations are used to access multiple memory cells, then device complexity is reduced, but access bandwidth and productivity are limited

Engineering Contradiction:
Improveaccess bandwidthVSAvoidaccess operation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the memory array into multiple independently controllable blocks, each with its own word lines and bit lines. This allows simultaneous access to multiple blocks in parallel, increasing access bandwidth while maintaining manageable complexity through modular organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a block selection dimension by adding block select lines that control access to different memory blocks. This additional control dimension enables parallel access operations across multiple blocks without significantly increasing the complexity of individual cell access operations

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If high bias voltages are applied to access memory cells, then access speed is improved, but unintentional thresholding of non-target cells increases

Engineering Contradiction:
Improveaccess speedVSAvoidselectivity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies different voltage levels to different regions of the memory array through block select lines. Target blocks receive high bias voltages for fast access, while non-target blocks receive low or zero bias voltages, preventing unintentional thresholding. This localized voltage control maintains both speed and selectivity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The block select lines act as intermediaries between the control logic and the memory cells. They transmit and condition voltage signals to specific blocks, enabling precise control over which cells receive high bias voltages and which remain protected from unintentional thresholding

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If parallel access to multiple memory cells is implemented, then access bandwidth is increased, but the risk of unintentionally thresholding non-target cells increases

Engineering Contradiction:
Improveaccess bandwidthVSAvoidunintentional thresholding
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements local quality control by applying high bias voltages only to specifically selected memory blocks while keeping other blocks at low voltage. This spatial differentiation allows parallel access to multiple target cells without causing unintentional thresholding in non-target cells, thus increasing bandwidth while maintaining selectivity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances access bandwidth and scalability by enabling parallel access to multiple memory cells, reducing the time required for operations and minimizing the risk of unintentionally thresholding non-target cells, thereby improving the performance of phase change memory devices.

Implementation Method 1

Devices incorporating chalcogenide materials, e.g., ovonic threshold switches and phase change storage elements

Methodology Applied
Scientific EffectPhase transition: Phase Change

Implementation Method 2

threshold-switching phase change memory cells

Methodology Applied
Scientific EffectThreshold switching:

Data Source

PatentUS10854287B2Accessing memory cells in parallel in a cross-point array
Publication Date: 2020.12.01 MICRON TECHNOLOGY INC
  • US10854287B2 patent drawing
  • US10854287B2 patent drawing
  • US10854287B2 patent drawing

AI summary

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.