Parallel Memory Access Synchronization via Tokens
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Solution Overview
Problem
In dataflow architectures, synchronizing accesses to shared memory is crucial to prevent write operations from proceeding before all read operations have completed, ensuring semantically correct results, but existing methods struggle with efficiently managing concurrent memory access operations.
Innovation Solution
A pipelined circuit design is created from a high-level language specification, where a data dependency graph is used to identify sequences of operations bounded by write operations, with read operations accessing memory in parallel and requiring synchronization tokens, and a synchronize component is employed to ensure proper synchronization between read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read operations access memory in parallel to improve performance, then productivity increases, but synchronization complexity increases to ensure correct ordering
Solution Approach 1:
The patent segments memory access operations into distinct read and write operations, each managed by separate synchronization tokens. This segmentation allows parallel execution of read operations while maintaining clear synchronization boundaries through the token mechanism, resolving the contradiction between parallelism and synchronization complexity.
Solution Approach 2:
The patent introduces synchronization tokens as intermediary objects that mediate between read and write operations. These tokens act as signals to coordinate access ordering without requiring complex synchronization logic, enabling parallel memory accesses while maintaining correctness through a simple yet effective intermediary mechanism.
2Productivity
If write operations proceed quickly to improve throughput, then productivity increases, but correctness decreases if reads haven't completed
Solution Approach 1:
The patent implements preliminary action by requiring read operations to complete and release their synchronization tokens before write operations can proceed. This preliminary completion of reads ensures data correctness is established before writes occur, maintaining reliability while allowing efficient throughput through the token-based coordination mechanism.
Solution Approach 2:
The synchronization tokens provide feedback signals that indicate when read operations have completed and when write operations should proceed. This feedback mechanism ensures correct ordering of memory accesses by using the completion status of reads as a prerequisite for writes, thereby maintaining correctness without unnecessary delays.
Data Source
AI summary
Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.