Parallel Memory Address Mapping via Segmented Tables
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Solution Overview
Problem
Current data processing systems face challenges in efficiently mapping logical addresses to physical addresses across multiple memory systems operating in parallel, leading to inefficiencies in data storage and retrieval operations.
Innovation Solution
A data processing system is designed with two memory systems, each maintaining a table of physical addresses corresponding to logical addresses, where controllers in each system generate physical addresses from logical addresses and determine operations based on table existence checks, allowing for simultaneous and efficient data operations across both systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory systems operate in parallel to increase data processing capacity, then productivity is improved, but device complexity increases due to the need for managing multiple address mapping tables
Solution Approach 1:
The patent divides the address mapping management into separate segments for each memory system. Each memory system maintains its own address mapping table independently, eliminating the need for a centralized management structure and reducing overall system complexity while maintaining parallel processing capability
Solution Approach 2:
The patent implements a universal hash function that can be applied across all memory systems to generate physical addresses from logical addresses. This multi-functional approach allows each memory system to operate independently using the same algorithm, simplifying management while maintaining productivity
2Speed
If physical addresses are generated simultaneously in multiple memory systems to improve operation speed, then speed is improved, but manufacturing precision requirements increase to ensure correct address mapping
Solution Approach 1:
The patent pre-allocates specific physical address ranges to each memory system and establishes predetermined hash functions for each system before operation begins. This preliminary configuration ensures that simultaneous address generation in parallel memory systems will not produce conflicts, maintaining both speed and accuracy
Solution Approach 2:
The patent modifies the hash function parameters specific to each memory system (such as using different prime numbers or offset values) to ensure that simultaneous operations across multiple systems produce unique physical addresses. This parameter differentiation maintains mapping accuracy while enabling parallel operation
Data Source
AI summary
A data processing system may include at least two memory systems including first and second memory systems to which a logical address and a command are applied in parallel from a host. The first memory system may store a plurality of first physical addresses for physically indicating a plurality of first pages included in a first non-volatile memory device as a first table, and determines whether to perform a preset operation corresponding to the applied command according to whether a physical address generated by performing a preset operation on the applied logical address exists in the first table, and the second memory system may store a plurality of second physical addresses for physically indicating a plurality of second pages included in a second non-volatile memory device as a second table, and determines whether to perform the preset operation corresponding to the applied command according to whether a physical address generated by performing the preset operation on the applied logical address exists in the second table.