Parallel Memory Bank Overwriting for Resilient Data Erasure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data erasure methods are time-consuming and lack resilience, as they typically require sequential access to memory locations and are prone to incomplete erasure, posing security risks due to the potential recovery of unwanted data.
Innovation Solution
A data erasure system that concurrently overwrites data on multiple memory banks independently using an erasure module, combined with a backup power system to ensure uninterrupted operation during power disruptions, thereby reducing erasure time and enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential overwriting of memory banks is performed by a processor, then data erasure is achieved, but the erasure time is excessive and productivity is low
Solution Approach 1:
The memory system is divided into multiple independent banks that can be processed simultaneously. The erasure module is segmented to handle different banks in parallel, with each bank having its own control logic and data bus, enabling concurrent overwriting operations across multiple banks rather than sequential processing
Solution Approach 2:
The system transitions from one-dimensional sequential processing to multi-dimensional parallel processing by utilizing multiple memory banks and multiple dedicated data buses. This dimensional expansion allows simultaneous erasure operations across different banks, dramatically increasing throughput and reducing total erasure time
2Reliability
If sequential processing is used for memory erasure, then system complexity is kept simple, but reliability and resilience are poor due to potential delays and incomplete erasure
Solution Approach 1:
The erasure module is divided into multiple independent processing units, each responsible for a specific memory bank. Each unit has its own control logic and can operate independently, ensuring that failures or delays in one unit do not affect others, thereby improving overall reliability and resilience of the erasure process
Solution Approach 2:
Each memory bank is equipped with dedicated control logic and data buses tailored to its specific erasure requirements. This localized configuration allows each bank to be optimized for reliable erasure while maintaining independence, so that the complexity is distributed rather than centralized, improving overall system reliability
3Productivity
If a processor writes to and reads from one bank at a time via a shared bus, then device complexity is reduced, but the erasure operation is time-consuming and productivity suffers
Solution Approach 1:
The bus structure is segmented into multiple dedicated data buses, with each bus assigned to a specific memory bank. This segmentation eliminates bus contention and allows simultaneous data transfers to multiple banks, dramatically increasing erasure throughput. The complexity of having multiple buses is offset by the removal of bus arbitration logic needed for shared bus access
Solution Approach 2:
The system transitions from a single shared bus to a multi-bus architecture, expanding the data transfer dimension from one to many parallel channels. This allows concurrent erasure operations across multiple banks without the bottlenecks of sequential bus access, significantly improving productivity despite increased bus structure complexity
Data Source
AI summary
A data erasure system (100) comprising a memory (101) comprising a plurality of banks (101a-n). The data erasure system (100) further comprises a processor (102) configured to write data to and/or read data from one of the plurality of banks (101a-n) at a time. The data erasure system (100) further comprises an erasure module (106) configured to perform an erasure operation by overwriting data on two or more of the plurality of banks (101a-n) concurrently, wherein overwriting data on one of the two or 10 more banks (101a-n) is independent of overwriting data on another of the two or more banks (101a-n).