Memory Block Erase Scheme for Non-Adjacent Parallel Erasing
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Solution Overview
Problem
Existing memory devices face inefficiencies in erasing multiple blocks, particularly when using odd-even-division erasing methods, leading to prolonged erasing times for non-adjacent blocks, which can be further exacerbated when erasing multiple discontinuous blocks.
Innovation Solution
A flexible multi-block erasing scheme that allows for the simultaneous selection and erasure of multiple blocks within the same period of time, utilizing a common source line for applying erase voltage and subsequent verify voltage application to reduce total erasing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If odd-even-division erasing method is used for multiple blocks, then erasing can be performed in an organized manner, but total erasing time is prolonged
Solution Approach 1:
The patent merges multiple block erasing operations into a single simultaneous operation. By selecting multiple blocks (including non-adjacent blocks) and applying erase voltage to a common source line connected to all selected blocks, the patent performs erasing of multiple blocks in parallel within the same time period, thereby reducing total erasing time while maintaining organized control through the selection circuit.
2Reliability
If multiple discontinuous blocks are erased sequentially, then each block can be properly erased, but erasing time is significantly extended
Solution Approach 1:
The patent combines multiple discontinuous block erasing operations into a single simultaneous operation. The selection circuit enables selection of non-adjacent blocks, and the common source line allows erase voltage to be applied to all selected blocks at the same time. This parallel erasing approach maintains reliable erasing of each block while dramatically reducing the total time required compared to sequential erasing.
Solution Approach 2:
The patent transitions from one-dimensional sequential erasing (processing blocks one after another) to multi-dimensional parallel erasing (processing multiple blocks simultaneously). By utilizing the common source line architecture and selection circuit capabilities, the system can select and erase multiple blocks across different positions in the memory device at the same time, effectively adding a temporal dimension to the erasing process.
3Loss of time
If simultaneous multi-block erasing is implemented, then total erasing time is reduced, but control complexity increases
Solution Approach 1:
The patent employs a universal common source line that serves multiple blocks simultaneously. This single source line can be connected to any number of blocks through the selection circuit, allowing the same hardware infrastructure to handle both single-block and multi-block erasing operations. The selection circuit provides multi-functional control, enabling flexible selection of adjacent or non-adjacent blocks without requiring separate dedicated circuits for each block.
4Ease of operation
If traditional block selection method is used, then simple control is maintained, but non-adjacent blocks cannot be selected simultaneously
Solution Approach 1:
The selection circuit provides universal control capability that can select any combination of blocks including adjacent and non-adjacent blocks. This multi-functional selection mechanism maintains operational simplicity through a unified selection interface while enabling versatile block selection patterns. The circuit can adapt to different selection scenarios (single block, multiple adjacent blocks, multiple non-adjacent blocks) using the same control logic and hardware infrastructure.
Data Source
AI summary
In certain aspects, a method of operating a memory device is disclosed. A first block and a second block are selected from the memory device. The memory device includes a plurality of blocks including the first block, the second block, and a third block located between the first and second blocks in a plane of the memory device. The third block is unselected while the first and second blocks are being selected. A first erase operation is performed on the first and second blocks in a first period of time.