Parallel Memory Bus Interfaces Using Higher-Order Modulation
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Solution Overview
Problem
The speed at which storage bandwidth increases cannot keep pace with the performance improvement of processors, leading to inefficiencies in data access and transmission.
Innovation Solution
A data processing system utilizing a high-speed parallel bus connecting a computing subsystem and a memory subsystem, with bus interfaces capable of higher-order modulation and demodulation, allowing for efficient data transmission and flexible memory module configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional storage bandwidth is used, then device complexity is reduced, but data transmission speed cannot keep pace with processor performance improvement
Solution Approach 1:
The patent applies parameter changes by transitioning from conventional modulation to higher-order modulation schemes (such as PAM4 instead of PAM2), which increases the data transmission speed by encoding more bits per symbol. This parameter change in the modulation order allows the storage interface to achieve higher bandwidth rates that can keep pace with processor performance improvements.
Solution Approach 2:
The patent implements dimensionality change by moving from serial communication to parallel communication architecture. By using multiple lanes for simultaneous data transmission, the system achieves higher aggregate bandwidth through spatial multiplication, effectively increasing data transmission speed without proportionally increasing per-lane complexity.
2Productivity
If higher-order modulation is implemented, then data transmission rate increases, but signal demodulation difficulty increases
Solution Approach 1:
The patent introduces an intermediary equalization mechanism between the transmitted signal and the received signal. The equalizer compensates for channel distortions and inter-symbol interference that become more severe with higher-order modulation, making the demodulation process more reliable by restoring the signal to a more detectable state before decoding.
Solution Approach 2:
The patent implements feedback mechanisms through training sequences and channel estimation procedures. The receiver uses known training symbols to characterize the channel response and adjust equalization parameters, creating a closed-loop system that adapts to channel conditions and reduces demodulation difficulty despite using higher-order modulation schemes.
Data Source
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AI summary
A data processing system and method are provided. The system includes a computing subsystem (100) and a memory subsystem (200), and the computing subsystem (100) and the memory subsystem (200) are connected through a high-speed parallel bus (300). In the computing subsystem (100), a processor may be connected to one end of the high-speed parallel bus (300) via a first bus interface (110). The processor transmits, via the first bus interface (110) to the memory subsystem (200) through the high-speed parallel bus (300), data that needs to be sent; and receives, via the first bus interface (110), data transmitted through the high-speed parallel bus (300). A second bus interface (210) in the memory subsystem (200) is connected to the high-speed parallel bus (300). The memory subsystem (200) receives, via the second bus interface (210), data transmitted through the high-speed parallel bus (300); and transmits, via the second bus interface (210), data to the computing subsystem (100) through the high-speed parallel bus (300). A data transmission rate of the high-speed parallel bus (300) is higher, the bus interfaces at the two ends of the high-speed parallel bus (300) can implement higher-order modulation, and a larger amount of data can be transmitted in a periodicity, to improve efficiency of data transmission between the computing subsystem (100) and the memory subsystem (200).