Parallel Memory Circuit Signal Routing for Image Sensor Miniaturization

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Solution Overview

Problem

Existing image sensor technologies require a significant area for signal output circuits due to the need for separate arrangements and outputs of signals from memory arrays, which complicates miniaturization and integration.

Innovation Solution

A memory circuit configuration with a word line and bit line arrangement that allows for parallel signal transmission, enabling the reading of most significant to least significant bits as one word without the need for additional signal arrangement circuits, thus reducing the area required for signal output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a word line is disposed to cross a plurality of bit lines in a horizontal direction to read signals from memory circuits, then signals can be read from multiple bit memories, but a signal output circuit is required to arrange and output signals which increases the area of the signal output circuit

Engineering Contradiction:

Improvesignal reading capabilityVSAvoidsignal output circuit area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges the functions of the word line and bit line by disposing them in parallel rather than crossing them. The word line extends in the first direction to read signals from memories arranged in that direction, while the bit line includes a digit line connected to memories arranged in the second direction and an output line extending in the first direction. This merging eliminates the need for a separate signal arrangement circuit, thereby reducing the signal output circuit area while maintaining signal reading capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The bit line is designed with dual functionality: it serves as both a digit line connected to multiple memories arranged in the second direction and as an output line that transmits signals in the first direction. This multi-functional design allows the bit line to perform both data access and signal output functions, eliminating the need for additional dedicated output arrangement circuits and reducing overall circuit area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If separate signal arrangement circuits are used to output signals from memory arrays, then signals can be properly arranged and output, but the overall size of the image sensor increases

Engineering Contradiction:

Improvesignal output reliabilityVSAvoidimage sensor size

Core Design Contradiction:

ReliabilityVSVolume of moving object

Solution Approach 1:

The patent combines the signal reading and output functions into a single integrated structure where the word line and bit line work together. The word line reads signals from memories in the first direction, and the bit line's output line simultaneously transmits these signals without requiring separate arrangement circuits. This integration maintains signal output reliability while reducing the overall image sensor size by eliminating redundant circuitry.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the signal arrangement function from the traditional crossing word line and bit line configuration and integrates it directly into the parallel bit line structure. The output line of the bit line is designed to directly transmit signals from the digit line without requiring external arrangement circuits, thereby removing unnecessary components and reducing image sensor volume.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If a traditional crossing word line and bit line configuration is used, then signals can be read from multiple memories, but additional signal arrangement circuits are required which complicates the circuit structure

Engineering Contradiction:

Improvememory signal readingVSAvoidcircuit structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the word line and bit line into a parallel configuration where the bit line's output line directly handles signal transmission. This integration eliminates the need for separate signal arrangement circuits that would be required in a traditional crossing configuration, thereby simplifying the overall circuit structure while maintaining the ability to read signals from multiple memories efficiently.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Instead of the traditional crossing configuration where word lines and bit lines intersect requiring complex signal routing, the patent inverts the approach by using parallel extension. The word line extends in the first direction to access memories, and the bit line's output line also extends in the first direction to transmit signals, creating a simplified linear flow that reduces circuit complexity.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11678087B2Memory circuit and semiconductor device

Publication Date: 2023.06.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory circuit includes a memory array, a word line, and a bit line. The memory array includes a plurality of memories arranged in a matrix shape in a first direction and a second direction perpendicular to the first direction. The word line extends in the first direction and reads signals from the plurality of memories arranged in the first direction. The bit line includes a digit line connected to the plurality of memories arranged in the second direction and an output line connected to the digit line and extending in the first direction and transmits a signal from a memory corresponding to the word line to the output line as the word line reads a signal.