Parallel Memory Compression Lanes for Low-Latency Data Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current computing systems face performance bottlenecks due to the CPU being occupied for data compression and decompression operations, leading to delays in processing and retrieval of data across multiple software applications, especially when dealing with limited local cache memory storage.
Innovation Solution
A computing system with a processor that includes a compression unit and a decompression unit, utilizing multiple hardware lanes to perform compression and decompression operations in parallel, allowing the CPU to remain available for other tasks while the data is processed, using a combination of statistical-based and dictionary-based algorithms to efficiently manage data compression and decompression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the CPU performs data compression and decompression operations, then data storage efficiency is improved, but processor availability and system throughput deteriorate
Solution Approach 1:
The patent extracts the compression and decompression functions from the CPU by implementing dedicated hardware compression and decompression units within the memory controller. This allows the CPU to remain available for other tasks while data compression and decompression operations are performed independently by specialized hardware components.
Solution Approach 2:
The patent introduces an intermediary memory compression unit that acts as a mediator between the CPU and memory system. This unit handles compression and decompression operations, allowing the CPU to issue memory access requests without being blocked by compression overhead, thereby improving both storage efficiency and processor availability.
2Quantity of substance
If data is compressed to reduce storage requirements, then memory capacity utilization is improved, but access latency increases due to compression/decompression overhead
Solution Approach 1:
The patent implements preliminary compression of data before it is written to memory, so that when data is read back, it is already in compressed form and can be decompressed quickly by the dedicated hardware unit. This preliminary action reduces the time penalty associated with compression by performing it during the write operation rather than during read operations.
Solution Approach 2:
The patent replaces the software-based compression and decompression mechanisms with hardware-based units that operate in parallel with the memory access operations. This substitution eliminates the sequential overhead of software processing and allows compression/decompression to occur concurrently with memory transactions, significantly reducing access latency.
3Reliability
If multiple processors wait for CPU to complete compression operations, then data integrity is maintained, but system throughput and parallel processing capability deteriorate
Solution Approach 1:
The patent segments the compression and decompression operations into independent hardware units that can process data in parallel with other processors. This segmentation allows multiple processors to access memory simultaneously without being blocked by a single CPU's compression operations, maintaining data integrity through dedicated hardware pathways while improving overall system throughput.
Solution Approach 2:
The patent implements self-service compression and decompression capabilities within the memory controller that operate independently of the CPU. Each memory access request can be handled by the memory compression unit without requiring CPU intervention, allowing multiple processors to service their own data needs simultaneously while maintaining data integrity through hardware-enforced protocols.
Data Source
AI summary
Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.