Parallel Duty Correction in Memory Chips for Stable Clock Training
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Solution Overview
Problem
Existing memory devices face challenges in reducing duty correction circuit (DCC) training time and duty cycle degradation due to memory chip variations and channel variations, leading to performance degradation.
Innovation Solution
A memory device and controller configuration that includes multiple memory chips with duty correction circuits and duty sensing circuits, allowing for parallel duty correction operations during a dedicated training period, which corrects duty cycle mismatches and maintains performance even with increasing numbers of memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are used to increase storage capacity, then storage capacity is improved, but duty cycle degradation increases due to chip variation and channel variation
Solution Approach 1:
The patent divides the duty correction function into separate duty correction circuits for each memory chip. Each chip has its own DCC that independently corrects duty cycle based on local comparison signals, allowing parallel operation without mutual interference and maintaining duty cycle stability across multiple chips.
Solution Approach 2:
The patent implements feedback mechanisms where duty sensing circuits monitor the duty cycle of clock signals and generate comparison signals that are fed back to duty correction circuits. This closed-loop feedback enables automatic adjustment and correction of duty cycle deviations caused by chip and channel variations.
2Measurement precision
If duty correction is performed sequentially for each memory chip, then duty cycle accuracy is improved, but training time increases
Solution Approach 1:
The patent segments the duty correction system into independent parallel units, with each memory chip having its own duty correction circuit that operates independently. This segmentation enables simultaneous duty correction for multiple chips without requiring sequential processing, thereby reducing total training time while maintaining accuracy.
Solution Approach 2:
The patent performs duty correction operations during a dedicated training period before normal operation begins. By preparing and correcting duty cycles in advance during this preliminary phase, the system ensures accurate duty cycles are established before data transfer operations start, avoiding time loss during actual operation.
3Reliability
If duty correction circuit is added to each memory chip, then duty cycle correction capability is improved, but device complexity increases
Solution Approach 1:
The patent designs duty correction circuits with universal functionality that can operate across multiple memory chips using the same clock signal. Each DCC is configured to receive comparison signals and generate corrected clock signals in a standardized manner, allowing the same circuit design to be replicated across chips without increasing overall system complexity.
Solution Approach 2:
The patent combines the duty sensing circuit and duty correction circuit into an integrated duty correction system. The comparison signal generation and duty cycle adjustment functions are merged into a cohesive circuit architecture that operates efficiently without requiring separate independent circuits for each function.
4Measurement precision
If training period is extended to improve duty cycle correction accuracy, then duty cycle accuracy is improved, but productivity decreases
Solution Approach 1:
The patent performs duty cycle correction during a dedicated training period before normal data transfer operations begin. By completing all necessary duty cycle adjustments and corrections in advance, the system ensures optimal duty cycle accuracy is achieved before productivity-critical operations start, minimizing impact on overall data transfer efficiency.
Solution Approach 2:
The patent implements duty correction operations in periodic intervals during the training phase, allowing the system to establish stable duty cycles through repeated measurement and adjustment cycles. This periodic approach ensures thorough correction while keeping the training period manageable and not excessively long.
Data Source
AI summary
A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.