Parallel Memory Channel ECC for Bandwidth Preservation
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Solution Overview
Problem
Standard DRAM memory with ECC is not suitable for systems requiring high storage capacity and bandwidth due to cost, design limitations, and availability issues, leading to reduced bandwidth when implementing error correction, as it requires dual accesses for write and read operations.
Innovation Solution
A method for writing and reading data to multiple channels of memory, where data is written or read to one channel and the corresponding error correction code is simultaneously written or read to a different channel, allowing for parallel operations across multiple channels to maintain bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code is implemented in standard DRAM memory, then data integrity is improved, but bandwidth is reduced due to dual write/read accesses
Solution Approach 1:
The invention segments the error correction operations by distributing data and ECC code across multiple independent memory channels. Data is written to one channel while ECC code is written to another channel simultaneously, allowing parallel operations that prevent bandwidth reduction.
Solution Approach 2:
The invention transitions from single-channel sequential operations to multi-channel parallel operations. By utilizing multiple memory channels simultaneously, the system performs data and ECC code operations in parallel across different channels, effectively adding a dimensional aspect to the error correction process.
2Reliability
If dual write/read accesses are used for error correction, then data integrity is improved, but channel bandwidth is reduced by half
Solution Approach 1:
The invention merges data and ECC code operations into a single unified write/read cycle by utilizing multiple channels. Instead of performing separate sequential operations on the same channel, both data and ECC code are transferred simultaneously across different channels, combining the functionality while maintaining full bandwidth utilization.
Solution Approach 2:
The system performs preliminary organization of data and ECC code assignment to different channels before the actual transfer operation. This preliminary arrangement enables simultaneous parallel transfers, ensuring that bandwidth is not reduced while maintaining error correction capabilities.
3Reliability
If standard DRAM-ECC memory is used, then error correction capability is improved, but cost and design availability are worsened
Solution Approach 1:
The invention introduces a memory controller as an intermediary that implements the error correction logic. Instead of requiring specialized DRAM-ECC memory chips with built-in ECC logic, the controller performs the error correction functions, making the system compatible with standard, widely available memory modules while reducing cost and design complexity.
Data Source
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AI summary
A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.