Parallel Redundancy Analysis for Memory Fault Repair
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Solution Overview
Problem
Existing redundancy analysis methods in memory systems suffer from long latency and low repair speed, leading to increased memory production time and potential yield loss due to inefficient fault detection and repair processes.
Innovation Solution
A redundancy analysis method utilizing parallel processing with a parallel computing device, such as a GPU, to allocate faults in memory systems by performing redundancy allocation on combinations of spare areas, allowing for efficient fault detection and repair through simultaneous testing and analysis with automatic test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential redundancy analysis is performed on each memory, then analysis accuracy is maintained, but analysis time increases significantly
Solution Approach 1:
The patent segments the redundancy analysis process by dividing fault combinations into multiple groups and processing each group in parallel using separate threads. This allows simultaneous analysis of multiple memory faults without compromising accuracy, as each thread independently evaluates its assigned fault combinations using the same sequential analysis logic.
Solution Approach 2:
The patent implements partial parallelization by processing only a portion of fault combinations in parallel at any given time, managing thread execution to handle subsets of the total fault analysis. This approach achieves significant time reduction while maintaining the rigorous sequential analysis required for accurate redundancy evaluation.
2Productivity
If parallel processing is applied to redundancy analysis, then analysis speed increases, but system complexity increases
Solution Approach 1:
The patent divides the parallel processing system into independent thread modules, each handling specific fault combination groups. This segmentation allows the complex parallel system to be managed through modular, standardized thread units that can be independently controlled and monitored, reducing overall system complexity.
Solution Approach 2:
The patent introduces a thread management mechanism that acts as an intermediary between the parallel threads and the fault analysis logic. This mediator coordinates thread execution, manages fault combination distribution, and aggregates results, thereby simplifying the control of multiple parallel processes without requiring complex inter-thread communication.
3Reliability
If more fault combinations are analyzed simultaneously, then repair rate accuracy improves, but memory storage requirements increase
Solution Approach 1:
The patent segments fault combinations into distinct groups that are processed in parallel by different threads. Each thread manages a specific subset of fault combinations, allowing comprehensive analysis of multiple combinations simultaneously while using minimal memory per thread. This segmentation eliminates the need to load all fault combinations into memory at once.
Solution Approach 2:
The patent processes fault combinations in partial batches through multiple thread executions rather than loading all combinations into memory simultaneously. Each thread handles a manageable subset of combinations, achieving high repair rate accuracy through comprehensive analysis while keeping memory usage at levels suitable for implementing the invention.
Data Source
AI summary
A redundancy analysis method of replacing a faulty part of a memory with at least one spare according to the present embodiment includes: acquiring fault information of the memory; and redundancy-allocating the fault with combinations of the spares to correspond to combination codes corresponding to the combinations of the spares, in which, the redundancy-allocating with the combination of the spare areas includes performing parallel processing on each combination of the spares.