Parallel Memory Writes Using In-Array Compute Sensing Circuitry
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Solution Overview
Problem
Existing memory systems face inefficiencies in processing performance and power consumption due to the need for serial data transfers and external processing resources, which increase latency and power consumption, especially in processor-in-memory (PIM) devices.
Innovation Solution
Implementing a memory device with integrated sensing circuitry and logic circuitry on pitch with memory cells, allowing parallel writing to multiple locations within the memory array, reducing the need for external data transfers and enabling simultaneous execution of compute functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred serially between external processing resources and memory array, then device complexity is reduced, but processing performance and data throughput deteriorate
Solution Approach 1:
The patent combines processing resources with the memory array by implementing processing elements directly within the memory device structure. This integration allows simultaneous data processing and storage operations, eliminating the need for serial data transfers between separate memory and processing units, thereby improving processing performance while maintaining manageable device complexity through unified architecture
Solution Approach 2:
The memory device is designed to perform multiple functions including data storage, data processing, and data transfer operations within a single integrated structure. The processing elements can execute computational tasks directly on stored data, enabling the memory system to serve both as storage medium and processing unit, thus enhancing productivity without requiring separate dedicated processing resources
2Use of energy by stationary object
If data is transferred externally between memory and processing resources, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent extracts the processing function from external processing resources and embeds it directly within the memory device. This extraction eliminates the need for continuous data movement between memory and external processors, reducing power consumption associated with data transfers while consolidating functionality into a single integrated device that maintains acceptable complexity levels
3Speed
If processing resources are implemented externally to memory array, then device complexity is reduced, but latency increases
Solution Approach 1:
The patent implements processing elements nested within the memory device structure, where processing units are embedded among the memory cells and access circuits. This nesting allows processing operations to be performed immediately on data without external transfer delays, significantly reducing latency while the integrated design keeps overall device complexity manageable through shared resources and compact layout
Data Source
AI summary
The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.