Parallel Memory Interface Address Translation for Non-Volatile Storage
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Solution Overview
Problem
Conventional data transfer methods between volatile and non-volatile memory in computer systems involve multiple hardware and software interactions, leading to increased latencies and reduced bandwidth due to the need for data translation and multiple intervening elements.
Innovation Solution
A computer memory device with a parallel memory interface and address translation circuit that directly receives logical addresses from the system memory controller, translates them to physical addresses, and stores data in non-volatile memory, eliminating the need for storage controllers and reducing data translation requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred from volatile memory to non-volatile memory using conventional methods with storage controllers and multiple hardware interactions, then data can be stored in non-volatile memory, but data transfer rates decrease and latencies increase
Solution Approach 1:
The patent extracts and eliminates the storage controller from the data path between volatile and non-volatile memory. By removing this intermediate hardware component, the system achieves direct memory-to-memory communication, thereby increasing data transfer rates and reducing the number of hardware interactions required for data transfer operations.
Solution Approach 2:
The patent merges the volatile and non-volatile memory systems into a unified memory architecture that operates as a single integrated unit. This consolidation allows the system to manage both memory types through a single interface (the memory controller), eliminating the need for separate storage controllers and reducing protocol translation overhead, thus improving transfer rates and reducing latencies.
2Productivity
If multiple hardware and software interactions are used for data translation between volatile and non-volatile memory, then data can be transferred between memory types, but bandwidth is reduced
Solution Approach 1:
The patent removes unnecessary data translation steps by eliminating the storage controller that performed protocol conversions and address translations. The memory controller directly manages both volatile and non-volatile memory, allowing data to be transferred with minimal translation requirements, thereby increasing effective bandwidth.
Solution Approach 2:
The memory controller is designed to universally manage both volatile and non-volatile memory types through a single interface. This multi-functional capability allows the controller to handle data transfer operations for both memory types without requiring separate translation pathways, thus maximizing bandwidth utilization and reducing the number of translation steps needed.
3Loss of time
If storage controllers are used to manage data transfer to non-volatile memory, then data can be stored reliably, but host CPU involvement increases and latencies increase
Solution Approach 1:
The patent extracts the storage controller function from the data path and integrates it into the memory controller. This eliminates an entire layer of hardware and software interactions that previously required host CPU involvement for coordination, thereby reducing latency and freeing up CPU resources for other tasks.
Solution Approach 2:
The memory controller is empowered to autonomously manage data transfer operations between volatile and non-volatile memory without requiring host CPU intervention. The controller handles address translation, data routing, and transfer coordination independently, enabling self-service operation that reduces both latency and CPU involvement.
Data Source
AI summary
A method of storing data is provided. The method includes receiving commands from a system memory controller of a computer system. The commands include logical addresses and are received by a computer memory device comprising a parallel memory interface operatively coupled to the system memory controller and operatively coupled to a non-volatile memory. The method further includes responding to the commands by translating the received logical addresses to corresponding physical addresses of the non-volatile memory, receiving data from the system memory controller by the parallel memory interface, and storing the data at memory locations of the non-volatile memory corresponding to the physical addresses.