Parallel Multi-Plane Memory Operations Using Multiple Microcontrollers

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Solution Overview

Problem

Existing non-volatile memories face performance limitations due to the lack of efficient distributed control mechanisms for multiple planes, leading to suboptimal operation speeds during single and multi-plane operations.

Innovation Solution

A memory system with multiple planes and microcontrollers that perform distributed execution of control operations, including voltage, row circuit, and page buffer array control, enhancing parallel operation capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single microcontroller controls multiple planes sequentially, then device complexity is reduced, but operational speed and productivity deteriorate due to inability to perform parallel operations

Engineering Contradiction:
Improveoperational speedVSAvoidcontrol structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control function is segmented by dividing the single microcontroller into multiple independent microcontrollers (at least two), where each microcontroller can independently control different planes or different operations simultaneously. This segmentation enables parallel control of multiple planes, resolving the contradiction between operational speed and device complexity by distributing control tasks across multiple processing units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple microcontrollers are merged into a coordinated control system that manages multiple planes simultaneously. The microcontrollers work in parallel to perform program, read, and erase operations across different planes at the same time, achieving improved productivity while maintaining manageable system complexity through standardized control interfaces.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If multiple microcontrollers are introduced for distributed control, then operational performance and parallel processing improve, but device complexity increases

Engineering Contradiction:
Improveparallel operation capabilityVSAvoidmicrocontroller coordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Each microcontroller is designed with universal control capabilities that can manage different planes and operation types (program, read, erase). This multi-functionality reduces the need for specialized control logic for each plane, thereby limiting the increase in device complexity while maximizing parallel operation benefits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of time

If distributed control is implemented across multiple microcontrollers, then time efficiency for multi-plane operations improves, but control mechanism complexity worsens

Engineering Contradiction:
Improveoperation completion timeVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system performs preliminary setup by assigning specific planes to specific microcontrollers before operations begin. This pre-configuration of control relationships establishes a fixed mapping between microcontrollers and planes, reducing the complexity of real-time coordination while enabling efficient parallel execution of operations across multiple planes.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250299740A1Memory including multiple planes
Publication Date: 2025.09.25 SK HYNIX INC
  • US20250299740A1 patent drawing
  • US20250299740A1 patent drawing
  • US20250299740A1 patent drawing

AI summary

Disclosed is a memory including a plurality of planes, and a plurality of microcontrollers, and during a specific operation of a selected plane, among the plurality of planes, at least two microcontrollers, among the plurality of microcontrollers, perform distributed execution of control operations on the selected plane.