Parallel Memory Module Assignment for Internet Switches
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Solution Overview
Problem
High-speed packet switches face challenges in scalability and performance due to high memory bandwidth requirements, segregation of memory space, and centralized control, which impede their ability to handle bursty data traffic effectively.
Innovation Solution
A method for assigning memory modules to incoming packets using a sliding-window architecture with decentralized control, employing self-routing parameters (i, j, k) and a parameter assignment circuit that utilizes counters, tables, and processors to determine available memory locations, allowing for efficient memory allocation and reduced bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shared-memory based switching systems are used to improve throughput performance under heavy traffic, then throughput performance is improved, but scalability is restricted due to high memory bandwidth requirements and centralized control
Solution Approach 1:
The shared memory space is segmented into multiple independent memory modules, each with its own memory controller. This segmentation allows the system to scale by adding more memory modules without creating a single point of control, thereby improving both throughput performance and scalability simultaneously.
Solution Approach 2:
The patent transitions from a centralized control architecture to a distributed control architecture by adding the dimension of parallel memory controllers. Each memory controller operates independently to manage its own memory module, enabling the system to scale horizontally while maintaining high throughput performance under heavy traffic conditions.
2Device complexity
If memory space is segregated to simplify control, then control complexity is reduced, but memory bandwidth efficiency deteriorates due to memory conflicts
Solution Approach 1:
Each memory controller independently manages its own memory module without requiring centralized coordination. The self-routing parameters embedded in packets enable memory controllers to autonomously allocate memory locations, reducing control complexity while minimizing memory conflicts through decentralized decision-making that improves memory bandwidth efficiency.
3Device complexity
If centralized control is used to simplify memory allocation, then control structure is simplified, but performance degrades as system size increases
Solution Approach 1:
The centralized control function is segmented and distributed to multiple independent memory controllers, each managing a specific memory module. This segmentation allows the system to maintain simple local control structures while achieving high overall performance through parallel operation of multiple controllers, preventing performance degradation as system size increases.
Solution Approach 2:
Each memory controller is designed as a universal, multi-functional unit that can independently handle memory allocation, arbitration, and management for its assigned memory module. This universality allows the system to scale by adding identical controller modules, maintaining simple control structures while improving performance through parallel processing capabilities.
4Productivity
If memory bandwidth is increased to handle more packets, then packet processing capacity is improved, but system cost and complexity increase
Solution Approach 1:
The system segments memory bandwidth resources across multiple independent memory modules, each accessed by its own controller. This segmentation allows packet processing capacity to scale by adding memory modules rather than increasing the bandwidth of a single centralized memory system, thereby improving capacity while keeping individual controller complexity manageable.
Solution Approach 2:
The patent increases packet processing capacity by adding spatial dimension through multiple parallel memory controllers and modules, rather than increasing the temporal bandwidth of a single memory system. This dimensional approach allows capacity scaling without proportionally increasing system complexity, as each added module operates independently with its own simple control logic.
Data Source
AI summary
Systems and methods are described for high-speed memory assignment schemes for routing packets in a sharable parallel memory module based switch system. A method includes receiving a parameter, determining availability of memory location, determining if an available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available. Systems of the present invention provides hardware and/or software based components for implementing the steps of receiving a parameter, determining available memory location, determining if available memory location is pre-assigned, and assigning a packet a parameter if the memory location is available.