Parallel Memory Page Testing with On-Chip State Machines
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Solution Overview
Problem
The semiconductor industry faces significant challenges in reducing the time and cost associated with testing integrated circuit memory chips, particularly memory chips, as a substantial portion of the manufacturing cost is attributed to the lengthy and resource-intensive testing processes.
Innovation Solution
The method involves dividing memory elements into banks and pages, using onboard state machines to write and compare test patterns in parallel, measuring programming times, and incrementally adjusting voltages to achieve optimal programming within specified limits, thereby reducing testing time and identifying operational voltages for each page.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential testing methods are used for memory chips, then testing thoroughness is maintained, but testing time becomes excessively long and cost increases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank further divided into multiple pages. This segmentation enables parallel testing of multiple pages simultaneously across different banks, dramatically reducing overall testing time while maintaining comprehensive test coverage of all memory cells.
Solution Approach 2:
The invention combines multiple testing operations into a single integrated process. Multiple pages are tested in parallel using shared test circuits and control logic, merging what would traditionally be sequential operations into concurrent execution, thereby improving productivity without sacrificing testing thoroughness.
2Productivity
If higher programming voltages are applied to increase programming speed, then programming time is reduced, but device complexity and power consumption increase
Solution Approach 1:
The test circuits perform preliminary measurements of programming time at various voltage levels before final programming operations. This preliminary characterization allows the system to determine optimal voltage settings that achieve required programming speeds without unnecessarily high voltages, balancing speed requirements with energy efficiency.
Solution Approach 2:
The testing system dynamically adjusts programming voltage based on measured performance characteristics. By monitoring programming times and adjusting voltages adaptively, the system optimizes programming speed while avoiding excessive voltage application, thereby reducing unnecessary power consumption and heat generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces testing time, allows for efficient trimming of devices to operate at lower voltages, and minimizes the need for redundant memory elements, thereby lowering overall production costs and improving device reliability.
Implementation Method 1
the programming operation requires relatively high voltages for what is known as Fowler-Nordheim tunneling across the tunnel oxide to occur, and thus set the individual bits to either binary one or zero
Data Source
AI summary
A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.