Parallel Memory Redundancy Analysis via Queue System
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory device testing and redundancy analysis processes are time-consuming and costly due to sequential processing of test patterns and redundancy analysis, leading to inefficiencies in identifying and repairing defective memory cells in large arrays.
Innovation Solution
The introduction of a queue system that allows for parallel processing of test patterns and redundancy analysis, enabling asynchronous evaluation and reuse of previous test results, thereby reducing waiting times and optimizing the use of redundant rows and columns for repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential processing of test patterns and redundancy analysis is used, then processing simplicity is maintained, but testing time and cost increase
Solution Approach 1:
The testing system is divided into separate functional modules: a test pattern generator that applies test patterns to the memory device, a fail capture memory that stores test results, and a redundancy analyzer that processes fails. These modules can operate independently and in parallel, with the test pattern generator and redundancy analyzer working simultaneously on different test patterns, thereby increasing testing speed without requiring complete system redesign
Solution Approach 2:
A queue data structure is introduced as an intermediary between the test pattern generator and the redundancy analyzer. The queue stores fail information from multiple test patterns, allowing the redundancy analyzer to process fails asynchronously without waiting for each test pattern to complete. This mediator enables parallel processing while maintaining data integrity and proper ordering of operations
2Reliability
If redundancy analysis waits for each test pattern to complete, then data accuracy is ensured, but waiting time increases
Solution Approach 1:
Test results from multiple test patterns are captured and stored in the fail capture memory before the redundancy analysis begins. The queue pre-loads fail information from ongoing test patterns, so when the redundancy analyzer needs data, it is already available. This preliminary capture of data ensures accuracy while eliminating waiting time, as the analyzer processes pre-captured fails without pausing for test completion
3Measurement precision
If multiple test patterns are run to thoroughly test memory devices, then test coverage is improved, but testing cost and time increase
Solution Approach 1:
The system maintains continuous testing operations by overlapping test pattern application with redundancy analysis. While the test pattern generator applies multiple test patterns continuously to the memory device, the redundancy analyzer simultaneously processes fails from previous test patterns using the queue. This continuous parallel operation ensures thorough defect detection coverage while maximizing testing efficiency, as no time is lost waiting for analysis to complete between test patterns
Data Source
AI summary
A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.