Parallel Memory Transistors for Phase Change Integration Density
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Solution Overview
Problem
Conventional phase change memory cell structures face challenges in achieving high integration density and stable operation due to reduced memory size, leading to decreased drivability of selection switches, increased risk of heat-induced data destruction, and expanded memory cell area, which affects the reliability of read/write operations.
Innovation Solution
A semiconductor device design featuring two memory cell transistors connected in parallel between a memory element and a bit-line, allowing for adjustable driving current and reduced circuit area, with a layout that omits isolation regions between transistors to enhance drivability and prevent data destruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the memory cell size is increased to obtain sufficient heat quantity for phase change, then the drivability of the selection switch is improved, but the memory integration density is reduced
Solution Approach 1:
The patent merges two memory cell transistors into a single shared transistor structure. Both transistors share the same gate electrode and source/drain regions, allowing the combined structure to deliver sufficient current for phase change while occupying less area than two separate transistors would require. This merging resolves the contradiction by achieving the needed power output without proportionally increasing the area.
Solution Approach 2:
The shared transistor structure serves multiple functions simultaneously - it acts as the selection switch for both memory cells, provides the necessary current drive for phase change operation, and reduces the overall cell area. This multi-functionality allows the same structure to address both the power requirement and the integration density requirement.
2Quantity of substance
If the memory cell size is reduced to increase integration density, then the memory capacity is improved, but the drivability of the selection switch is lowered
Solution Approach 1:
By combining two transistors into a shared structure with common source/drain regions and gate, the patent achieves better current drive capability than a single small transistor could provide. The merged structure effectively pools the current capability while occupying minimal additional area, thus improving drivability without sacrificing integration density.
3Reliability
If isolation regions are added between transistors to prevent heat-induced data destruction, then the reliability is improved, but the circuit area is expanded
Solution Approach 1:
The patent merges adjacent transistors by removing isolation regions between them, creating a shared structure with common source/drain regions. This eliminates the need for isolation regions while maintaining reliability through the shared structure design that inherently controls heat distribution. The circuit area is reduced because the merged transistors occupy less space than two separate transistors with isolation regions would require.
4Power
If the gate width is expanded to obtain sufficient heat quantity, then the current capability is improved, but the memory cell area is largely expanded
Solution Approach 1:
Instead of expanding a single transistor's gate width to increase current capability, the patent merges two transistors into a shared structure. This approach achieves the needed current capability through the combined effect of two transistor channels working together, while the overall area remains smaller than what would be required for a single wide-gate transistor providing equivalent current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed and high-integration semiconductor operations by improving drivability, reducing circuit area, and minimizing heat-induced disturbances between memory cells, thereby enhancing the stability and efficiency of read/write operations.
Implementation Method 1
a phase change memory in which a difference in resistance value between an amorphous state (reset) of a phase change material and a polycrystalline state (set) thereof is stored as data
Implementation Method 2
Joule heat generated when a predetermined amount of current is caused to flow for a predetermined time is utilized in order to electrically cause the phase change
Data Source
AI summary
For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.