Parallel Transistor Miller Clamping With Auxiliary Gate Paths
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Solution Overview
Problem
Existing driver chips cannot effectively perform Miller clamping on parallel switching transistors due to limited current absorption capability and asynchronous ON/OFF issues, leading to potential accidental turn-on and damage to the transistors.
Innovation Solution
A Miller clamping device is introduced, comprising a driver chip with a built-in Miller clamping circuit and auxiliary Miller clamping circuits connected between the gates of parallel switching transistors and the built-in Miller clamping circuit, allowing Miller currents to flow to a DC voltage, thereby enhancing current absorption and preventing accidental turn-on.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a built-in Miller clamping circuit is used in the driver chip, then the Miller clamping function is provided, but the current absorption capability is insufficient for parallel switching transistors
Solution Approach 1:
The clamping function is segmented by providing individual auxiliary Miller clamping circuits for each switching transistor in parallel. Each auxiliary circuit independently clamps the Miller current from its corresponding transistor, distributing the current absorption task across multiple parallel paths rather than relying on a single built-in circuit.
Solution Approach 2:
The auxiliary Miller clamping circuits are merged with the built-in Miller clamping circuit to form a composite clamping system. The auxiliary circuits connect to the same clamping terminal as the built-in circuit, combining their current absorption capabilities to handle the total Miller current from all parallel switching transistors.
2Device complexity
If the built-in Miller clamping circuit is used alone, then the circuit structure is simple, but the Miller current conduction path resistance is too high for effective clamping
Solution Approach 1:
The Miller current conduction path is segmented into multiple parallel paths by introducing auxiliary clamping circuits. Each auxiliary circuit provides a dedicated low-resistance path from its corresponding switching transistor gate to the clamping terminal, reducing the equivalent resistance of the overall conduction path.
Solution Approach 2:
Multiple auxiliary Miller clamping circuits are created as copies of a basic auxiliary clamping circuit design. Each copy is connected to a different switching transistor gate, providing identical low-resistance clamping paths for each transistor, thereby reducing the overall equivalent resistance through parallel connection.
3Quantity of substance
If auxiliary Miller clamping circuits are added for each switching transistor, then the current absorption capability is amplified, but the device complexity increases
Solution Approach 1:
Multiple auxiliary Miller clamping circuits are merged by connecting them to a common clamping terminal on the driver chip. This shared terminal allows the auxiliary circuits to work together as a unified system, amplifying the total current absorption capability while avoiding the need for separate independent clamping systems for each transistor.
Solution Approach 2:
The auxiliary Miller clamping circuits are designed with universal applicability, using the same circuit topology and components for each transistor. This standardized design reduces overall system complexity by reusing proven circuit patterns rather than designing custom solutions for each transistor, while still providing enhanced current absorption capability.
Data Source
AI summary
The present invention provides a Miller clamping device for parallel switching transistors and a driver comprising the same. The Miller clamping device includes: a driver chip including an output terminal and a built-in Miller clamping circuit with a Miller clamping terminal, the output terminal of the driver chip being configured to output a pulse width modulation signal; and a plurality of auxiliary Miller clamping circuits, each of the auxiliary Miller clamping circuits being connected between a gate of a corresponding switching transistor and the Miller clamping terminal of the built-in Miller clamping circuit. When the built-in Miller clamping circuit is triggered for Miller clamping, a Miller current generated by the corresponding switching transistor flows to a first direct-current (DC) voltage through a corresponding auxiliary Miller clamping circuit. The Miller clamping device of the present invention can perform Miller clamping on the parallel switching transistors and reduce the circuit cost.