Parallel Mixed-Signal Equalization for High-Speed Links

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Solution Overview

Problem

Existing digital communication receiver designs face challenges in coping with increasing levels of intersymbol interference (ISI) and noise, especially at high symbol rates, as they struggle to accurately reconstruct data in long-reach channels.

Innovation Solution

A receiver embodiment featuring an array of sample and hold elements, linear equalizers, and decision elements that periodically sample and process analog receive signals to form weighted sums, derive symbol decisions, and employ feedback filters to combat ISI without amplifying noise, allowing for parallel output of symbol decisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If decision feedback equalizers are used to combat ISI, then intersymbol interference is reduced, but device complexity increases

Engineering Contradiction:
ImproveISI reductionVSAvoidequalizer complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The equalizer is divided into multiple parallel branches, each processing a different portion of the feedback signal. This segmentation allows the complex equalization task to be distributed across simpler parallel units, reducing the complexity of individual components while maintaining overall effectiveness in combating ISI.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a parallel dimension to the traditional sequential equalization process. By implementing multiple equalizer branches that operate simultaneously on different feedback paths, the system transforms a single complex processing task into multiple simpler parallel tasks, effectively managing complexity through dimensional expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If symbol rates are increased to improve productivity, then data transmission speed increases, but ISI levels increase

Engineering Contradiction:
Improvedata transmission speedVSAvoidISI levels
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The system employs feedback mechanisms where decisions about received symbols are fed back through filter branches to generate correction signals. This feedback loop continuously adapts the equalization parameters to counteract ISI caused by high symbol rates, allowing the system to maintain accuracy despite increased transmission speed.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The equalizer incorporates dynamic adjustment capabilities where filter coefficients and sampling timing are continuously adapted based on channel conditions. This dynamic behavior allows the system to respond to changing ISI characteristics at high symbol rates, maintaining optimal performance without fixed, rigid processing parameters.

Inventive Principle:
Principle #15Dynamics

3Productivity

If processing time is reduced to meet high symbol rates, then productivity improves, but measurement precision deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoidsymbol detection accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The system performs preliminary sampling of the incoming signal at multiple points before final decision-making. By capturing signal information in advance at different times and feeding it through parallel filter branches, the system prepares multiple processed versions of the signal simultaneously, enabling accurate decisions to be made within reduced time windows.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The equalizer operates with periodic sampling and processing cycles that are synchronized with the incoming signal rhythm. This periodic operation allows the system to maintain precise measurement and processing within each cycle while achieving high overall throughput through continuous, rhythmic processing at the optimal rate for the given symbol duration.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10728059B1Parallel mixed-signal equalization for high-speed serial link
Publication Date: 2020.07.28 CREDO TECHNOLOGY GROUP LTD
  • US10728059B1 patent drawing
  • US10728059B1 patent drawing
  • US10728059B1 patent drawing

AI summary

A receiver embodiment has an equalizer that includes: an array of sample and hold elements, an array of linear equalizers, and an array of decision elements. Each sample and hold element in the array periodically samples an analog receive signal with a respective phase to provide an associated held signal. Each linear equalizer in the array forms a periodically-updated weighted sum of the held signals from the array of sample and hold elements. Each decision element in the array derives at least one sequence of symbol decisions based on at least one of the periodically-updated weighted sums. The resulting sequences of symbol decisions are output in parallel.