Parallel ML Training for IC Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit design optimization techniques, such as Path Based Analysis, are runtime intensive due to exponential complexity, requiring days of analysis time for power reduction, and often resort to less accurate methods like Graph Based Analysis to reduce computational requirements.
Innovation Solution
The use of new machine learning and parallel training data generation techniques to divide circuit design data into smaller partitions, allowing for parallel training and optimization, significantly reducing runtime by localizing data and generating training data in a distributed manner across multiple machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive Path Based Analysis is used for power reduction, then power optimization accuracy is improved, but analysis runtime increases exponentially
Solution Approach 1:
The patent divides the circuit design into multiple partitions or blocks, allowing the machine learning model to process smaller segments independently and in parallel. This segmentation reduces the computational complexity from exponential to linear or polynomial, enabling exhaustive analysis to be applied to each partition without the full runtime penalty of analyzing the entire circuit at once.
Solution Approach 2:
The patent replaces traditional mechanical/computational analysis methods (exhaustive PBA, multi-voltage scaling) with a machine learning-based system. The ML model is trained on partitioned circuit data and then applied to optimize power consumption, substituting the computationally intensive analytical approach with a learned model that provides similar accuracy with dramatically reduced runtime.
2Productivity
If parallel processing is applied to Path Based_analysis, then processing speed is improved, but the circuit cannot be optimized during analysis
Solution Approach 1:
The patent performs preliminary actions by partitioning the circuit and training the machine learning model on these partitions before applying the model to optimize the full circuit. This preliminary training phase enables the system to subsequently optimize the circuit adaptively without requiring exhaustive re-analysis, combining the speed of parallel processing with the flexibility of optimization.
Solution Approach 2:
The machine learning model acts as an intermediary between the partitioned circuit analysis and the final circuit optimization. The model is trained on partitioned data (enabling parallel processing) and then serves as a mediator to apply optimization across the full circuit, bridging the gap between segmented analysis and holistic optimization.
Data Source
AI summary
A method of optimizing a power consumption of an integrated circuit design, includes dividing the integrated circuit design into N circuit partitions, supplying each circuit partition to a different one of N computer systems each associated with a different one of the N circuit partitions, training each of the N computer systems to reduce the power consumption of its associated circuit partition thereby to generate N training data, storing the N training data in a database, and applying the N training data to the integrated circuit design thereby to reduce the consumption of the integrated circuit design.