Parallel Look-Ahead Modular Multiplication for Chip Area Optimization
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Solution Overview
Problem
The existing ZDN method for modular multiplication in cryptography is inefficient due to limited shift values, leading to suboptimal use of multiplication look-ahead methods and increased chip area requirements, which hinders the implementation of more secure and efficient cryptography algorithms.
Innovation Solution
The proposed solution involves an iterative method that performs both exact and approximated three operand additions in parallel, using calculated look-ahead parameters to optimize shift values and reduce the need for larger shifters, thereby improving resource utilization and accelerating the modular multiplication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the ZDN method uses limited shift values for modular multiplication, then the chip area requirements are reduced, but the multiplication efficiency is degraded and resource utilization is suboptimal
Solution Approach 1:
The patent applies preliminary action by calculating look-ahead parameters in advance (before they are strictly needed) using an approximated intermediate result. This allows the exact three-operand addition to proceed without waiting for parameter calculation, thereby improving multiplication efficiency while maintaining the same chip area constraints.
Solution Approach 2:
The patent ensures continuity of useful action by performing both the exact three-operand addition and the look-ahead parameter calculation in parallel. This eliminates idle time in the iterative process, maintaining continuous productive operation without requiring additional chip area resources.
2Device complexity
If the ZDN method uses limited shift values, then existing shifter resources are sufficient, but the iteration process experiences idle time and reduced acceleration
Solution Approach 1:
The patent calculates look-ahead parameters preliminarily using an approximated intermediate result before the exact calculation is complete. This preliminary action eliminates the idle time that would otherwise occur while waiting for parameter calculation, without requiring more complex shifter resources.
Solution Approach 2:
The patent introduces a new dimension of calculation by performing both exact and approximated three-operand additions simultaneously. This dimensional expansion allows parameter calculation to proceed in parallel with the main computation, eliminating sequential idle time while keeping shifter resources unchanged.
3Productivity
If parallel calculation of look-ahead parameters is implemented, then multiplication acceleration is achieved, but calculation complexity increases
Solution Approach 1:
The patent segments the calculation process into two independent parallel paths: exact three-operand addition and approximated three-operand addition for parameter calculation. This segmentation enables multiplication acceleration through parallelism while managing complexity by dividing the workload into manageable, independent segments.
Solution Approach 2:
The patent uses an approximated intermediate result as an intermediary to facilitate parallel parameter calculation. This intermediary allows the system to proceed with parameter calculation before the exact result is available, achieving acceleration without significantly increasing overall calculation complexity.
Data Source
AI summary
A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is further implemented to perform an exact three operand addition in the current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters calculated for the current iteration step.