Parallel Modular Multiplier for Cryptosystem Speed
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Solution Overview
Problem
Conventional modular multipliers separate multiplication and reduction blocks, leading to inefficient hardware configuration and sequential arithmetic characteristics that slow down modular multiplication processing speed.
Innovation Solution
A modular multiplication method that performs parallel multiplication and reduction operations by dividing bit strings of the multiplicand and multiplier into lower and upper parts, allowing independent first and second arithmetic operations with corresponding reductions to calculate the modular multiplication result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiplication and reduction blocks are separated in conventional modular multipliers, then hardware configuration becomes simpler, but processing speed deteriorates due to sequential arithmetic characteristics
Solution Approach 1:
The patent merges multiplication and reduction operations into a unified arithmetic unit that processes both operations simultaneously. The arithmetic unit integrates a multiplier and a reduction mechanism, allowing parallel execution of multiplication and reduction blocks that were previously separated, thereby improving processing speed while maintaining reasonable hardware complexity through integrated design
Solution Approach 2:
The patent segments the modular multiplication process into multiple independent arithmetic operations that can be executed in parallel. By dividing the multiplication and reduction tasks into separate computational blocks within the arithmetic unit, the system can perform multiple operations simultaneously, improving productivity without requiring complete hardware separation
2Device complexity
If sequential arithmetic is used in conventional modular multipliers, then hardware design is simpler, but processing speed deteriorates due to time-consuming sequential operations
Solution Approach 1:
The patent performs preliminary reduction operations during the multiplication process itself rather than sequentially after multiplication completes. The reduction mechanism operates in parallel with the multiplier, performing reduction actions on intermediate results as they are generated, thereby reducing total processing time without significantly increasing hardware complexity
Solution Approach 2:
The patent ensures continuous useful action by overlapping multiplication and reduction operations in time. The arithmetic unit continuously performs both multiplication and reduction operations without idle sequential transitions, maintaining productive activity throughout the computation process and reducing overall arithmetic processing time
3Productivity
If parallel multiplication and reduction operations are implemented, then processing speed improves, but hardware configuration becomes more complex
Solution Approach 1:
The patent implements a universal arithmetic unit that performs multiple functions including multiplication, reduction, and data processing. This multi-functional design allows parallel operations to be executed within a single integrated unit rather than requiring separate dedicated hardware blocks, thereby improving processing speed while limiting the increase in hardware configuration complexity through functional integration
Data Source
AI summary
Provided are a modular multiplication method with an improved arithmetic operation, a modular multiplier and a cryptograph calculating system having the modular multiplier. The modular multiplication method comprises performing a first arithmetic operation including a first multiplication on a first bit string of a multiplicand and a first bit string of a multiplier and a first reduction for eliminating partial bits of the first multiplication result, performing a second arithmetic operation including a second multiplication on a second bit string of the multiplicand and a second bit string of the multiplier and a second reduction for eliminating partial bits of the second multiplication result, and calculating a modular multiplication result using the result of the first arithmetic operation and the result of the second arithmetic result. The first arithmetic operation and the second arithmetic operation are independently performed.