Parallel Motion Estimation Processor Architecture
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Solution Overview
Problem
High computational complexity in motion estimation for high-resolution video image processing, particularly in determining motion vectors, hinders real-time performance, and existing hardware implementations face challenges in reducing resource consumption and search time.
Innovation Solution
A parallel processor architecture with a matrix of elementary processors that computes partial match results in parallel, utilizing delay buffers and a sorting module to efficiently determine motion vectors by minimizing search iterations and resource usage, capable of implementing full search block matching motion estimation algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full search block matching method is used for motion estimation, then prediction accuracy is improved, but computational complexity increases
Solution Approach 1:
The search area is divided into multiple blocks, and each block is processed independently by separate processing elements. The current block is divided into multiple sub-blocks for parallel comparison with reference blocks, enabling the full search algorithm to be implemented with reduced computational burden through spatial segmentation of the processing task.
Solution Approach 2:
The patent introduces a temporal dimension by using delay buffers to store reference frame data, allowing parallel comparison across multiple reference blocks without re-reading from memory. This transforms the computational problem from a two-dimensional spatial search to a three-dimensional parallel processing operation, improving efficiency while maintaining full search accuracy.
2Speed
If hardware implementation is used for real-time performance, then processing speed is improved, but resource consumption increases
Solution Approach 1:
The processing elements are organized in a segmented array where each element handles a specific block comparison task. This segmentation allows the hardware to be scaled according to required performance, with each processing element being a reusable unit that can be instantiated multiple times in parallel, optimizing the ratio of processing speed to resource consumption.
Solution Approach 2:
Each processing element is designed as a universal unit capable of comparing any current block with any reference block from the search area. The delay buffers serve multiple purposes: storing reference data for current processing, providing data for subsequent processing stages, and enabling temporal parallelism. This multi-functionality reduces overall hardware resource requirements while maintaining high processing speed.
3Productivity
If parallel processing is used to reduce search time, then productivity is improved, but device complexity increases
Solution Approach 1:
The parallel processor is segmented into multiple identical processing elements arranged in an array, with each element handling a specific comparison task. This regular segmented structure simplifies the overall architecture by repeating a simple, well-defined unit rather than requiring a complex irregular structure, making the parallel system easier to design and implement while achieving high search speed.
Solution Approach 2:
Delay buffers serve as intermediaries between the processing elements and the reference frame memory, caching reference block data locally. This intermediary structure enables parallel processing by providing each processing element with immediate access to required reference data without contending for memory bandwidth, thereby increasing search speed while keeping the architecture relatively simple through localized data storage.
Data Source
AI summary
A parallel processor for motion estimation including: a matrix of elementary processors configured in rows and columns, local connections between the elementary processors for transmitting partial results, and row outputs for outputting a set of best match values (for example, SAD values), one value for each pixel row of a current block of image pixels; and search area delay buffers coupled to each row inputs, for accepting pixels of the search area as input and forming a reference block row. The processor further includes current block delay buffers coupled to each row inputs, for accepting pixels of the current block as input; a sum module coupled to the row outputs for computing a final match value from the row outputs; and a sorting module for sequentially selecting a best match value from the final match values outputted from the sum module, and generating a corresponding motion vector.